| /u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/arch/mips/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/arch/x86/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/arch/arm/dts/include/dt-bindings/clock/ |
| H A D | mt8183-clk.h | 84 #define CLK_TOP_APLL2_D8 48 macro
|
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 61 #define CLK_TOP_APLL2_D8 51 macro
|
| H A D | mt2712-clk.h | 82 #define CLK_TOP_APLL2_D8 51 macro
|
| H A D | mt6779-clk.h | 90 #define CLK_TOP_APLL2_D8 80 macro
|
| H A D | mt8183-clk.h | 115 #define CLK_TOP_APLL2_D8 79 macro
|
| H A D | mt8186-clk.h | 123 #define CLK_TOP_APLL2_D8 104 macro
|
| H A D | mt8192-clk.h | 120 #define CLK_TOP_APLL2_D8 108 macro
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 126 PLL_FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", CLK_APMIXED_APLL2, 1, 8),
281 CLK_TOP_APLL2_D8,
|
| H A D | clk-mt8516.c | 105 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
720 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
|
| H A D | clk-mt8512.c | 120 FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
218 CLK_TOP_APLL2_D8,
241 CLK_TOP_APLL2_D8,
|