Searched refs:CLK_TOP_APLL2_D4 (Results 51 - 57 of 57) sorted by relevance
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8512.c | 119 FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
211 CLK_TOP_APLL2_D4
240 CLK_TOP_APLL2_D4,
306 CLK_TOP_APLL2_D4,
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| H A D | clk-mt8365.c | 125 PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4),
280 CLK_TOP_APLL2_D4,
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| H A D | clk-mt8516.c | 104 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
719 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
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| H A D | clk-mt8518.c | 104 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
379 CLK_TOP_APLL2_D4
462 CLK_TOP_APLL2_D4,
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| H A D | clk-mt8183.c | 153 FACTOR(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4, CLK_PARENT_APMIXED),
507 CLK_TOP_APLL2_D4,
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8188-clk.h | 145 #define CLK_TOP_APLL2_D4 134 macro
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| H A D | mt8195-clk.h | 178 #define CLK_TOP_APLL2_D4 166 macro
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Completed in 236 milliseconds
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