Searched refs:CLK_TOP_APLL12_CK_DIV0 (Results 26 - 31 of 31) sorted by relevance
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| /u-boot/dts/upstream/include/dt-bindings/clock/ |
| H A D | mediatek,mt8365-clk.h | 122 #define CLK_TOP_APLL12_CK_DIV0 112 macro
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| H A D | mt8186-clk.h | 150 #define CLK_TOP_APLL12_CK_DIV0 131 macro
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| H A D | mediatek,mt8188-clk.h | 190 #define CLK_TOP_APLL12_CK_DIV0 179 macro
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt8365.c | 545 GATE_TOP2(CLK_TOP_AUD_I2S0_M, CLK_TOP_APLL12_CK_DIV0, 0),
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| H A D | clk-mt8516.c | 722 GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
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| H A D | clk-mt8518.c | 1442 GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
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