Searched refs:CLK_APMIXED_APLL1 (Results 51 - 58 of 58) sorted by relevance

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/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt6779-clk.h177 #define CLK_APMIXED_APLL1 12 macro
H A Dmt8183-clk.h20 #define CLK_APMIXED_APLL1 9 macro
H A Dmt8186-clk.h276 #define CLK_APMIXED_APLL1 12 macro
H A Dmt8192-clk.h309 #define CLK_APMIXED_APLL1 8 macro
H A Dmediatek,mt8188-clk.h309 #define CLK_APMIXED_APLL1 9 macro
H A Dmt8195-clk.h375 #define CLK_APMIXED_APLL1 16 macro
/u-boot/drivers/clk/mediatek/
H A Dclk-mt8516.c45 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
98 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
H A Dclk-mt8518.c45 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
99 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),

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