Searched refs:x5 (Results 51 - 75 of 546) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_sh_mask.h84 #define NB_NBCFG0_NB_PCI_CTRL__SErrDis__SHIFT 0x5
249 #define IOMMU_L2_0_IOMMU_STATUS__Reserved1__SHIFT 0x5
345 #define IOMMU_L2_0_IOMMU_CAP_RANGE__Reserved__SHIFT 0x5
358 #define IOMMU_L2_0_IOMMU_CAP_MISC__IOMMU_GVA_SIZE__SHIFT 0x5
373 #define IOMMU_L2_0_IOMMU_CAP_MISC_1__IOMMU_ARCH_MODE__SHIFT 0x5
447 #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__Reserved2__SHIFT 0x5
559 #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__BTM_W__SHIFT 0x5
635 #define IOMMU_L2_0_SMMU_MMIO_IDR5_W__GRAN16K_W__SHIFT 0x5
672 #define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
692 #define BIF_CFG_DEV0_RC0_STATUS__PCI_66_EN__SHIFT 0x5
[all...]
H A Dnbio_4_3_0_sh_mask.h729 #define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
971 #define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
1026 #define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
1348 #define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
1400 #define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
1497 #define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT 0x5
1546 #define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5
1664 #define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
2072 #define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
2137 #define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_4_0_0_sh_mask.h39 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
139 #define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
204 #define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
269 #define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
334 #define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
399 #define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
464 #define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
529 #define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
594 #define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
659 #define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
[all...]
/openbsd-current/gnu/usr.bin/binutils/gdb/
H A Darm-tdep.h79 #define INST_PL 0x5
/openbsd-current/sys/dev/pci/
H A Dixgb_ee.h45 #define EEPROM_WRITE_OPCODE 0x5 /* EEPROM write opcode */
H A Dpciide_acard_reg.h61 static const u_int8_t acard_udma_conf[] = {0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7};
/openbsd-current/sys/dev/microcode/aic7xxx/
H A Daicasm_insformat.h117 #define AIC_OP_ROL 0x5
/openbsd-current/sys/dev/pv/
H A Dpvreg.h76 #define CPUID_OFFSET_HYPERV_IMPL_LIMITS 0x5
/openbsd-current/sys/dev/pci/drm/i915/gvt/
H A Dedid.h63 NIDX_STOP = 0x5,
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/wafl/
H A Dwafl2_4_0_0_sh_mask.h30 #define PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS__CRCErr__SHIFT 0x5
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/xgmi/
H A Dxgmi_4_0_0_sh_mask.h30 #define XGMI0_PCS_GOPX16_PCS_ERROR_STATUS__CRCErr__SHIFT 0x5
H A Dxgmi_6_1_0_sh_mask.h33 #define PCS_XGMI3X16_PCS_ERROR_STATUS__CRCErr__SHIFT 0x5
/openbsd-current/gnu/llvm/lldb/source/Utility/
H A DARM64_DWARF_Registers.h22 x5, enumerator in enum:arm64_dwarf::__anon1558
H A DARM64_ehframe_Registers.h24 x5, enumerator in enum:arm64_ehframe::__anon1559
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu_v11_8_ppsmc.h39 #define PPSMC_MSG_SetDriverTableDramAddrLow 0x5
/openbsd-current/sys/dev/pci/drm/include/drm/
H A Di915_drm.h73 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
/openbsd-current/gnu/llvm/compiler-rt/lib/hwasan/
H A Dhwasan_tag_mismatch_riscv64.S113 sd x5, 40(sp)
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_enum.h33 NUMBER_SINT = 0x5,
49 CB_FMASK_DECOMPRESS = 0x5,
67 BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
97 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
107 CMASK_CLR01_F1 = 0x5,
125 CB_PERF_SEL_DRAWN_QUAD = 0x5,
353 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
383 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
391 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
405 CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
[all...]
H A Dgfx_8_1_enum.h33 NUMBER_SINT = 0x5,
49 CB_FMASK_DECOMPRESS = 0x5,
68 BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
98 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
108 CMASK_CLR01_F1 = 0x5,
131 CB_PERF_SEL_DRAWN_QUAD = 0x5,
538 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
568 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
576 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
590 CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
[all...]
H A Dgfx_8_0_enum.h33 NUMBER_SINT = 0x5,
49 CB_FMASK_DECOMPRESS = 0x5,
68 BLEND_ONE_MINUS_SRC_ALPHA = 0x5,
98 FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5,
108 CMASK_CLR01_F1 = 0x5,
131 CB_PERF_SEL_DRAWN_QUAD = 0x5,
529 CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5,
559 STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
567 CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5,
581 CPG_PERF_SEL_ME_PARSER_BUSY = 0x5,
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_3_0_1_enum.h59 IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
101 SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x5,
276 SRBM_PERF_SEL_MCB_BUSY = 0x5,
306 GRBM_GFX_INDEX_VCE0 = 0x5,
323 SRBM_GFX_CNTL_VCE0 = 0x5,
340 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
429 DBG_BLOCK_ID_SRBM = 0x5,
686 DBG_BLOCK_ID_IH_BY2 = 0x5,
808 DBG_BLOCK_ID_VC0_BY4 = 0x5,
870 DBG_BLOCK_ID_TCA_BY8 = 0x5,
[all...]
H A Doss_3_0_enum.h59 IH_PERF_SEL_CLIENT2_IH_STALL = 0x5,
211 SRBM_PERF_SEL_MCB_BUSY = 0x5,
241 GRBM_GFX_INDEX_VCE0 = 0x5,
258 SRBM_GFX_CNTL_VCE0 = 0x5,
275 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5,
338 ARRAY_PRT_TILED_THIN1 = 0x5,
370 CONFIG_2KB_ROW_OPT = 0x5,
436 DBG_CLIENT_BLKID_sx30 = 0x5,
596 DBG_BLOCK_ID_SRBM = 0x5,
830 DBG_BLOCK_ID_IH_BY2 = 0x5,
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/athub/
H A Dathub_1_0_sh_mask.h88 #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
175 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
352 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
735 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5
768 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5
1427 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
1572 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
1579 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
1586 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
1593 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
[all...]
H A Dathub_2_1_0_sh_mask.h76 #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5
481 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
546 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
622 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5
655 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5
1592 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
1733 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5
1740 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5
1747 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5
1754 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5
[all...]
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/smuio/
H A Dsmuio_13_0_2_sh_mask.h53 #define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5
115 #define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5
144 #define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5
198 #define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5
247 #define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5
271 #define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5
333 #define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5
362 #define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5
416 #define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5
465 #define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5
[all...]

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