Lines Matching refs:x5
39 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
139 #define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
204 #define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
269 #define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
334 #define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
399 #define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
464 #define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
529 #define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
594 #define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
659 #define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
724 #define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
789 #define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
854 #define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
919 #define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
984 #define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
1049 #define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
1114 #define SRE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
1179 #define UVD_MPBE0_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
1244 #define UVD_MPBE1_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
1309 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
1374 #define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1399 #define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1424 #define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1449 #define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1474 #define IME_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1499 #define MPC1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1524 #define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1549 #define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1574 #define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1599 #define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1624 #define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1649 #define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1674 #define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1699 #define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1724 #define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1749 #define UVD_MPBE0_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1764 #define UVD_MPBE1_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1779 #define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5
1804 #define AVM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
1857 #define CDEFE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
1910 #define DBR_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
1963 #define EFC_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2016 #define ENT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2069 #define IME_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2122 #define MPC1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2175 #define PPU_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2228 #define SAOE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2281 #define SCM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2334 #define SDB_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2387 #define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2440 #define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2493 #define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2546 #define SIT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2599 #define SMPA_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2652 #define SMP_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2705 #define SRE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2758 #define UVD_MPBE0_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2801 #define UVD_MPBE1_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2844 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
2931 #define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5
2982 #define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5
3035 #define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5
3095 #define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5
3118 #define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5
3141 #define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5
3371 #define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5
3557 #define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5
3585 #define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5
3594 #define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5
3603 #define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5
3629 #define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5
3694 #define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5
3814 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
3879 #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
3910 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
4047 #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
4856 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
5279 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5
5487 #define UVD_JMI_EJPEG_DROP__SCALAR_WR_DROP__SHIFT 0x5
5515 #define UVD_JMI_EJPEG_MEMCHECK_CLAMPING__SCALAR_WR_CLAMPING_EN__SHIFT 0x5
5561 #define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5
5620 #define UVD_JMI_CLEAN_STATUS__EJRBC_READ_CLEAN__SHIFT 0x5
5857 #define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5
5936 #define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5
5949 #define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5
5970 #define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5
5991 #define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5
6012 #define JPEG_MEMCHECK_SYS_INT_EN__JPEG2_RD_ERR_EN__SHIFT 0x5
6037 #define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH_RD_LO_ERR__SHIFT 0x5
6086 #define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH_RD_LO_ERR__SHIFT 0x5
6171 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5
6191 #define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5
6468 #define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5
6600 #define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5
6656 #define UVD_RAS_CNTL_PMI_ARB__ACK_JPEG0__SHIFT 0x5
6778 #define VCN_RB_ENABLE__RB4_EN__SHIFT 0x5
6797 #define VCN_RB_WPTR_CTRL__RB4_CS_EN__SHIFT 0x5
6908 #define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5
6950 #define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5
7010 #define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5
7048 #define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
7159 #define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5
7285 #define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5
7308 #define VCN_RAS_CNTL_MMSCH__MMSCH_PMI_EN__SHIFT 0x5
7324 #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
7366 #define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5
7397 #define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5
7533 #define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5
7584 #define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5
7641 #define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5
7698 #define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5
7749 #define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5
7806 #define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5
7863 #define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5
7912 #define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5
7961 #define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5
8010 #define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5