Searched refs:gfx (Results 26 - 50 of 93) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_gfx.h223 /* gfx configure feature */
404 /* gfx status */
415 /* gfx off */
418 uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
419 struct delayed_work gfx_off_delay_work; /* async work to set gfx block off */
457 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
458 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
459 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id) ((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid), (xcc_id)))
460 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx
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H A Daldebaran.c272 adev->gfx.rlc.funcs->resume(adev);
375 if (tmp_adev->gfx.ras &&
376 tmp_adev->gfx.ras->ras_block.ras_late_init) {
377 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev,
378 &tmp_adev->gfx.ras->ras_block.ras_comm);
H A Damdgpu_ring_mux.c337 struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
346 struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
355 struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
414 struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
417 if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) {
429 struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
440 struct amdgpu_ring_mux *mux = &adev->gfx.muxer;
H A Dgfx_v9_4_2.c433 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) {
465 for (se = 0; se < adev->gfx.config.max_shader_engines; se++)
493 int wb_size = adev->gfx.config.max_shader_engines *
501 if (!adev->gfx.compute_ring[0].sched.ready ||
502 !adev->gfx.compute_ring[1].sched.ready)
516 &adev->gfx.compute_ring[0],
522 adev->gfx.cu_info.number,
532 adev->gfx.cu_info.number * SIMD_ID_MAX * 2,
541 &adev->gfx.compute_ring[1],
547 adev->gfx
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H A Damdgpu_amdkfd_gfx_v10.c60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
146 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
147 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
303 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
304 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
309 spin_lock(&adev->gfx.kiq[0].ring_lock);
336 spin_unlock(&adev->gfx
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H A Dmes_v11_0.c877 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
878 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
902 ring = &adev->gfx.kiq[0].ring;
969 mtx_init(&adev->gfx.kiq[0].ring_lock, IPL_TTY);
971 ring = &adev->gfx.kiq[0].ring;
997 ring = &adev->gfx.kiq[0].ring;
1085 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1086 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1087 &adev->gfx.kiq[0].ring.mqd_ptr);
1093 amdgpu_ring_fini(&adev->gfx
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H A Damdgpu_amdkfd_gfx_v8.c60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
118 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
119 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
172 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
173 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
H A Damdgpu_amdkfd_gfx_v7.c66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
123 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
124 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
H A Dsoc15_common.h41 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
46 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
H A Dmes_v10_1.c803 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
804 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
863 mtx_init(&adev->gfx.kiq[0].ring_lock, IPL_TTY);
865 ring = &adev->gfx.kiq[0].ring;
891 ring = &adev->gfx.kiq[0].ring;
977 amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
978 &adev->gfx.kiq[0].ring.mqd_gpu_addr,
979 &adev->gfx.kiq[0].ring.mqd_ptr);
985 amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1041 mes_v10_1_kiq_setting(&adev->gfx
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H A Damdgpu_device.c522 adev->gfx.rlc.funcs &&
523 adev->gfx.rlc.funcs->is_rlcg_access_range) {
524 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
1978 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1979 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1980 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1981 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1982 adev->gfx.config.max_texture_channel_caches =
1984 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1985 adev->gfx
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H A Dgmc_v11_0.c288 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron)
297 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) &&
335 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;
336 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
339 spin_lock(&adev->gfx.kiq[0].ring_lock);
347 spin_unlock(&adev->gfx.kiq[0].ring_lock);
352 spin_unlock(&adev->gfx.kiq[0].ring_lock);
H A Damdgpu_amdkfd_arcturus.c283 * Helper used to suspend/resume gfx pipe for image post process work to set
290 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
291 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
H A Dgmc_v10_0.c339 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes &&
425 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring;
426 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
429 spin_lock(&adev->gfx.kiq[0].ring_lock);
437 spin_unlock(&adev->gfx.kiq[0].ring_lock);
442 spin_unlock(&adev->gfx.kiq[0].ring_lock);
H A Dgmc_v9_0.c575 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
847 if (adev->gfx.kiq[0].ring.sched.ready &&
956 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;
957 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
977 spin_lock(&adev->gfx.kiq[inst].ring_lock);
995 spin_unlock(&adev->gfx.kiq[inst].ring_lock);
1001 spin_unlock(&adev->gfx.kiq[inst].ring_lock);
1895 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2120 NUM_XCC(adev->gfx
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H A Dgfxhub_v1_2.c70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
427 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
466 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
524 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
573 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0);
H A Damdgpu_uvd_v4_2.c599 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
600 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
601 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Duvd_v5_0.c303 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
304 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
305 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Damdgpu_uvd_v3_1.c270 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
271 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
272 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
H A Damdgpu_display.c728 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
729 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes;
803 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
808 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
814 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) +
815 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se);
817 ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
819 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
H A Dvi.c537 * Returns the reference clock used by the gfx engine
756 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
758 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
760 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
762 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
780 return adev->gfx.config.gb_addr_config;
782 return adev->gfx.config.mc_arb_ramcfg;
816 return adev->gfx.config.tile_mode_array[idx];
834 return adev->gfx.config.macrotile_mode_array[idx];
H A Djpeg_v3_0.c350 adev->gfx.config.gb_addr_config);
352 adev->gfx.config.gb_addr_config);
/openbsd-current/sys/dev/pci/drm/amd/amdkfd/
H A Dkfd_crat.c1342 if (adev->gfx.config.gc_tcp_l1_size) {
1343 pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size;
1348 pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
1352 if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {
1354 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
1359 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1363 if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
1364 pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
1369 pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1373 if (adev->gfx
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/openbsd-current/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c217 adev->gfx.config.gb_addr_config_fields.num_pipes;
219 adev->gfx.config.gb_addr_config_fields.num_banks;
221 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
223 adev->gfx.config.gb_addr_config_fields.num_se;
225 adev->gfx.config.gb_addr_config_fields.max_compress_frags;
227 adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
230 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
360 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
405 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
407 ilog2(adev->gfx
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/openbsd-current/sys/dev/pci/drm/radeon/
H A Dradeon_ucode.h214 struct gfx_firmware_header_v1_0 gfx; member in union:radeon_firmware_header

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