Searched refs:pll (Results 51 - 75 of 120) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/dvb/frontends/
H A Ddib8000.c473 const struct dibx000_bandwidth_config *pll = state->cfg.pll; local
477 dib8000_write_word(state, 901, (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
480 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
481 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) | (1 << 3) | (pll->pll_range << 1) | (pll->pll_reset << 0);
484 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll
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H A Ddib0090.c194 /* pll is not locked locked */
196 dprintk("FE%d : Identification : pll is not yet locked", fe->id);
265 /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */
1188 const struct dib0090_pll *pll = state->current_pll_table_index; local
1233 pll = dib0090_pll_table;
1237 while (rf > pll->max_freq)
1238 pll++;
1240 state->current_pll_table_index = pll;
1255 if (pll->vco_band)
1262 lo5 |= (pll
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H A Ddib8000.h14 struct dibx000_bandwidth_config *pll; member in struct:dib8000_config
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/
H A Dsvgalib.c362 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) argument
369 ar = pll->r_max;
379 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
385 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
393 am = pll->m_min;
394 an = pll->n_min;
396 while ((am <= pll->m_max) && (an <= pll
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H A Dw100fb.c1067 static int w100_pll_adjust(struct w100_pll_info *pll) argument
1091 if (tf80 >= (pll->tfgoal)) {
1097 if (tf20 <= (pll->tfgoal))
1125 static int w100_pll_calibration(struct w100_pll_info *pll) argument
1129 status = w100_pll_adjust(pll);
1154 static int w100_pll_set_clk(struct w100_pll_info *pll) argument
1169 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M;
1170 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int;
1171 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac;
1172 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll
1192 struct w100_pll_info *pll = par->pll_table; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/radeon/
H A Dradeon_legacy_crtc.c682 struct radeon_pll *pll; local
705 pll = &rdev->clock.p2pll;
707 pll = &rdev->clock.p1pll;
709 pll->flags = RADEON_PLL_LEGACY;
711 pll->algo = PLL_ALGO_NEW;
713 pll->algo = PLL_ALGO_LEGACY;
716 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
718 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
730 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
745 pll
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H A Dradeon_legacy_tv.c46 /* tv pll setting for 27 mhz ref clk */
55 /* tv pll setting for 14 mhz ref clk */
242 struct radeon_pll *pll; local
246 pll = &rdev->clock.p2pll;
248 pll = &rdev->clock.p1pll;
251 *pll_ref_freq = pll->reference_freq;
256 if (pll->reference_freq == 2700)
261 if (pll->reference_freq == 2700)
413 struct radeon_pll *pll; local
417 pll
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/
H A Datyfb_base.c312 static int pll; variable
374 int pll, mclk, xclk, ecp_max; member in struct:__anon16242
446 par->pll_limits.pll_max = aty_chips[i].pll;
574 par->pll.ct.xres = 0;
578 par->pll.ct.xres = var->xres;
1301 var->bits_per_pixel, &par->pll);
1320 par->dac_ops->set_dac(info, &par->pll,
1322 par->pll_ops->set_pll(info, &par->pll);
1326 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
1448 /* dump non shadow CRTC, pll, LC
1509 union aty_pll pll; local
1832 union aty_pll *pll = &par->pll; local
1857 union aty_pll *pll = &par->pll; local
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H A Daty128fb.c401 struct aty128_pll pll; member in struct:aty128fb_par
521 * Functions to read from/write to the pll registers
1279 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par) argument
1300 div3 |= pll->feedback_divider;
1302 div3 |= post_conv[pll->post_divider] << 16;
1318 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, argument
1340 pll->post_divider = post_dividers[i];
1352 pll->feedback_divider = round_div(n, d);
1353 pll->vclk = vclk;
1356 "vclk_per: %d\n", pll
1364 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var) argument
1380 aty128_ddafifo(struct aty128_ddafifo *dsp, const struct aty128_pll *pll, u32 depth, const struct aty128fb_par *par) argument
1514 struct aty128_pll pll; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/intelfb/
H A Dintelfbhw.c660 struct pll_min_max *pll = &plls[index]; local
665 vco = pll->ref_clk * m / n;
868 struct pll_min_max *pll = &plls[index]; local
871 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
872 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
889 struct pll_min_max *pll = &plls[index]; local
906 if (p % 4 == 0 && p1 < pll->min_p1) {
910 if (p1 < pll
928 struct pll_min_max *pll = &plls[index]; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/riva/
H A Driva_hw.c620 unsigned int M, N, P, pll, MClk; local
622 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
623 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
809 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local
811 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
812 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 1
1072 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local
1117 unsigned int M, N, P, pll, MClk, NVClk; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath9k/
H A Dar5008_phy.c1014 u32 pll; local
1016 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1019 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1021 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1024 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1026 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1028 return pll;
1034 u32 pll; local
1036 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1039 pll |
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H A Dar9003_phy.c391 u32 pll; local
393 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
396 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
398 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
400 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
402 return pll;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2410/
H A Ds3c2410.c42 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5p6440/
H A Dmach-smdk6440.c42 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/matrox/
H A Dmatroxfb_Ti3026.c545 minfo->features.pll.vco_freq_min = 110000;
546 minfo->features.pll.ref_freq = 114545;
547 minfo->features.pll.feed_div_min = 2;
548 minfo->features.pll.feed_div_max = 24;
549 minfo->features.pll.in_div_min = 2;
550 minfo->features.pll.in_div_max = 63;
551 minfo->features.pll.post_shift_max = 3;
H A Dmatroxfb_maven.c209 static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll, argument
216 unsigned int fmin = pll->vco_freq_min / ctl->den;
226 fmax = pll->vco_freq_max / ctl->den;
230 for (p = 1; p <= pll->post_shift_max; p++) {
241 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
247 if (n < pll->feed_div_min)
249 if (n > pll->feed_div_max)
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/include/linux/
H A Dsvga.h117 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dclkgen_defs.h95 unsigned int pll : 1; member in struct:__anon8689
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-s3c24xx/include/plat/
H A Dcpu-freq-core.h109 * @pll: The PLL table entry for the current PLL settings.
122 struct cpufreq_frequency_table pll; member in struct:s3c_cpufreq_config
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2412/
H A Ds3c2412.c53 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2440/
H A Ds3c244x.c46 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/nouveau/
H A Dnv50_crtc.c268 struct pll_lims pll; local
277 ret = get_pll_limits(dev, reg, &pll);
281 if (pll.vco2.maxfreq) {
282 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
296 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
308 ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/video/cx18/
H A Dcx18-av-core.c446 int fsc, pll; local
449 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
450 pll /= pll_post;
452 pll / 1000000, pll % 1000000);
454 pll / 8000000, (pll / 8) % 1000000);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/jz4740/
H A Dclock.c313 .name = "pll",
323 .name = "pll half",
880 uint32_t pll; local
885 pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
886 } while (!(pll & JZ_CLOCK_PLL_STABLE));

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