Searched refs:pll (Results 26 - 50 of 120) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/cris/arch-v32/mach-fs/
H A Dcpufreq.c27 return clk_ctrl.pll ? 200000 : 6000;
50 clk_ctrl.pll = 1;
52 clk_ctrl.pll = 0;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/
H A Dradeon_base.c439 rinfo->pll.ref_clk = (*val) / 10;
443 rinfo->pll.sclk = (*val) / 10;
447 rinfo->pll.mclk = (*val) / 10;
583 rinfo->pll.ref_clk = xtal;
584 rinfo->pll.ref_div = ref_div;
585 rinfo->pll.sclk = sclk;
586 rinfo->pll.mclk = mclk;
604 rinfo->pll.ppll_max = 35000;
605 rinfo->pll.ppll_min = 12000;
606 rinfo->pll
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-s3c24xx/
H A Dclock.c44 #include <plat/pll.h>
H A Ds3c2410-cpufreq-utils.c63 __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
H A Ds3c2443-clock.c389 unsigned long pll; local
399 pll = get_mpll(mpllcon, xtal);
400 clk_msysclk.clk.rate = pll;
402 fclk = pll / get_fdiv(clkdiv0);
411 print_mhz(pll), print_mhz(fclk),
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/parisc/include/asm/
H A Drtc.h121 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
125 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-msm/
H A Dclock-7x30.h144 void pll_enable(uint32_t pll);
145 void pll_disable(uint32_t pll);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/nvidia/
H A Dnv_hw.c144 unsigned int pll, N, M, MB, NB, P; local
147 pll = NV_RD32(par->PMC, 0x4020);
148 P = (pll >> 16) & 0x07;
149 pll = NV_RD32(par->PMC, 0x4024);
150 M = pll & 0xFF;
151 N = (pll >> 8) & 0xFF;
157 MB = (pll >> 16) & 0xFF;
158 NB = (pll >> 24) & 0xFF;
162 pll = NV_RD32(par->PMC, 0x4000);
163 P = (pll >> 1
684 unsigned int M, N, P, pll, MClk, NVClk, memctrl; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/radeon/
H A Datombios_crtc.c470 struct radeon_pll *pll)
481 /* reset the pll flags */
482 pll->flags = 0;
487 pll->algo = PLL_ALGO_LEGACY;
489 pll->algo = PLL_ALGO_NEW;
492 pll->algo = PLL_ALGO_NEW;
494 pll->algo = PLL_ALGO_LEGACY;
501 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
505 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
507 pll
468 atombios_adjust_pll(struct drm_crtc *crtc, struct drm_display_mode *mode, struct radeon_pll *pll) argument
811 struct radeon_pll *pll; local
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c447 u32 pll; local
449 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
452 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
454 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
458 pll = 0x142c;
460 pll = 0x2850;
462 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
464 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
467 return pll;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/ar7/
H A Dclock.c62 u32 pll; member in struct:tnetd7300_clock
178 u32 pll = readl(&clock->pll); local
182 int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
202 if ((pll & PLL_MODE_MASK) == 0)
205 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
243 writel(4, &clock->pll);
244 while (readl(&clock->pll) & PLL_STATUS)
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/avr32/boards/atstk1000/
H A Datstk1002.c221 struct clk *pll; local
226 pll = clk_get(NULL, "pll0");
227 if (IS_ERR(pll))
230 if (clk_set_parent(gclk, pll)) {
239 clk_put(pll);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/sound/soc/codecs/
H A Dak4642.c280 u8 pll; local
284 pll = PLL2;
287 pll = PLL2 | PLL0;
290 pll = PLL2 | PLL1;
293 pll = PLL2 | PLL1 | PLL0;
296 pll = PLL3 | PLL2;
299 pll = PLL3 | PLL2 | PLL0;
304 snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
H A Dwm8955.c138 int Fref, int Fout, struct pll_factors *pll)
151 pll->outdiv = 1;
154 pll->outdiv = 0;
164 pll->n = Ndiv;
179 pll->k = K / 10;
181 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
243 struct pll_factors pll; local
277 clock_cfgs[sr].mclk, &pll);
137 wm8995_pll_factors(struct device *dev, int Fref, int Fout, struct pll_factors *pll) argument
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/radio/
H A Dtef6862.c109 u16 pll; local
116 pll = 1964 + ((f->frequency - TEF6862_LO_FREQ) * 20) / FREQ_MUL;
118 i2cmsg[1] = (pll >> 8) & 0xff;
119 i2cmsg[2] = pll & 0xff;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2410/
H A DMakefile19 obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/matrox/
H A Dmatroxfb_DAC1064.c180 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
580 minfo->features.pll.vco_freq_min = 62000;
581 minfo->features.pll.ref_freq = 14318;
582 minfo->features.pll.feed_div_min = 100;
583 minfo->features.pll.feed_div_max = 127;
584 minfo->features.pll.in_div_min = 1;
585 minfo->features.pll.in_div_max = 31;
586 minfo->features.pll.post_shift_max = 3;
715 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL);
725 matroxfb_g450_setclk(minfo, minfo->values.pll
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-davinci/
H A Dtnetv107x.c115 #define define_pll_clk(cname, pll, divmask, base) \
117 .num = pll, \
134 #define define_pll_div_clk(pll, cname, div) \
135 static struct clk pll##_##cname##_clk = { \
136 .name = #pll "_" #cname "_clk",\
137 .parent = &pll_##pll##_clk, \
639 int pll; local
655 for (pll = 0; pll < N_PLLS; pll
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H A Dclock.h119 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/include/asm-generic/
H A Drtc.h209 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
213 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dconfig_defs.h92 unsigned int pll : 1; member in struct:__anon9093
100 unsigned int pll : 1; member in struct:__anon9094
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/cris/include/arch-v32/arch/hwregs/
H A Dconfig_defs.h92 unsigned int pll : 1; member in struct:__anon8226
100 unsigned int pll : 1; member in struct:__anon8227
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2416/
H A Dclock.c25 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/alpha/include/asm/
H A Dcore_marvel.h268 #define IO7_PLL_RNGA(pll) (((pll) >> 3) & 0x7)
269 #define IO7_PLL_RNGB(pll) (((pll) >> 6) & 0x7)
/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dhndchipc.c86 uint32 rev, cap, pll, baud_base, div; local
98 pll = cap & CC_CAP_PLL_MASK;
103 if (CCPLL_ENAB(sih) && pll == PLL_TYPE1) {
105 baud_base = si_clock_rate(pll,

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