1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26#include <drm/drmP.h> 27#include <drm/drm_crtc_helper.h> 28#include <drm/radeon_drm.h> 29#include <drm/drm_fixed.h> 30#include "radeon.h" 31#include "atom.h" 32#include "atom-bits.h" 33 34static void atombios_overscan_setup(struct drm_crtc *crtc, 35 struct drm_display_mode *mode, 36 struct drm_display_mode *adjusted_mode) 37{ 38 struct drm_device *dev = crtc->dev; 39 struct radeon_device *rdev = dev->dev_private; 40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 41 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 43 int a1, a2; 44 45 memset(&args, 0, sizeof(args)); 46 47 args.ucCRTC = radeon_crtc->crtc_id; 48 49 switch (radeon_crtc->rmx_type) { 50 case RMX_CENTER: 51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; 53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; 55 break; 56 case RMX_ASPECT: 57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 59 60 if (a1 > a2) { 61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; 63 } else if (a2 > a1) { 64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; 66 } 67 break; 68 case RMX_FULL: 69 default: 70 args.usOverscanRight = radeon_crtc->h_border; 71 args.usOverscanLeft = radeon_crtc->h_border; 72 args.usOverscanBottom = radeon_crtc->v_border; 73 args.usOverscanTop = radeon_crtc->v_border; 74 break; 75 } 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 77} 78 79static void atombios_scaler_setup(struct drm_crtc *crtc) 80{ 81 struct drm_device *dev = crtc->dev; 82 struct radeon_device *rdev = dev->dev_private; 83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 84 ENABLE_SCALER_PS_ALLOCATION args; 85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 86 87 enum radeon_tv_std tv_std = TV_STD_NTSC; 88 bool is_tv = false, is_cv = false; 89 struct drm_encoder *encoder; 90 91 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 92 return; 93 94 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 95 /* find tv std */ 96 if (encoder->crtc == crtc) { 97 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 98 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 99 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 100 tv_std = tv_dac->tv_std; 101 is_tv = true; 102 } 103 } 104 } 105 106 memset(&args, 0, sizeof(args)); 107 108 args.ucScaler = radeon_crtc->crtc_id; 109 110 if (is_tv) { 111 switch (tv_std) { 112 case TV_STD_NTSC: 113 default: 114 args.ucTVStandard = ATOM_TV_NTSC; 115 break; 116 case TV_STD_PAL: 117 args.ucTVStandard = ATOM_TV_PAL; 118 break; 119 case TV_STD_PAL_M: 120 args.ucTVStandard = ATOM_TV_PALM; 121 break; 122 case TV_STD_PAL_60: 123 args.ucTVStandard = ATOM_TV_PAL60; 124 break; 125 case TV_STD_NTSC_J: 126 args.ucTVStandard = ATOM_TV_NTSCJ; 127 break; 128 case TV_STD_SCART_PAL: 129 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 130 break; 131 case TV_STD_SECAM: 132 args.ucTVStandard = ATOM_TV_SECAM; 133 break; 134 case TV_STD_PAL_CN: 135 args.ucTVStandard = ATOM_TV_PALCN; 136 break; 137 } 138 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 139 } else if (is_cv) { 140 args.ucTVStandard = ATOM_TV_CV; 141 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 142 } else { 143 switch (radeon_crtc->rmx_type) { 144 case RMX_FULL: 145 args.ucEnable = ATOM_SCALER_EXPANSION; 146 break; 147 case RMX_CENTER: 148 args.ucEnable = ATOM_SCALER_CENTER; 149 break; 150 case RMX_ASPECT: 151 args.ucEnable = ATOM_SCALER_EXPANSION; 152 break; 153 default: 154 if (ASIC_IS_AVIVO(rdev)) 155 args.ucEnable = ATOM_SCALER_DISABLE; 156 else 157 args.ucEnable = ATOM_SCALER_CENTER; 158 break; 159 } 160 } 161 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 162 if ((is_tv || is_cv) 163 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 164 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 165 } 166} 167 168static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 169{ 170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 171 struct drm_device *dev = crtc->dev; 172 struct radeon_device *rdev = dev->dev_private; 173 int index = 174 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 175 ENABLE_CRTC_PS_ALLOCATION args; 176 177 memset(&args, 0, sizeof(args)); 178 179 args.ucCRTC = radeon_crtc->crtc_id; 180 args.ucEnable = lock; 181 182 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 183} 184 185static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 186{ 187 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 188 struct drm_device *dev = crtc->dev; 189 struct radeon_device *rdev = dev->dev_private; 190 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 191 ENABLE_CRTC_PS_ALLOCATION args; 192 193 memset(&args, 0, sizeof(args)); 194 195 args.ucCRTC = radeon_crtc->crtc_id; 196 args.ucEnable = state; 197 198 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 199} 200 201static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 202{ 203 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 204 struct drm_device *dev = crtc->dev; 205 struct radeon_device *rdev = dev->dev_private; 206 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 207 ENABLE_CRTC_PS_ALLOCATION args; 208 209 memset(&args, 0, sizeof(args)); 210 211 args.ucCRTC = radeon_crtc->crtc_id; 212 args.ucEnable = state; 213 214 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 215} 216 217static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 218{ 219 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 220 struct drm_device *dev = crtc->dev; 221 struct radeon_device *rdev = dev->dev_private; 222 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 223 BLANK_CRTC_PS_ALLOCATION args; 224 225 memset(&args, 0, sizeof(args)); 226 227 args.ucCRTC = radeon_crtc->crtc_id; 228 args.ucBlanking = state; 229 230 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 231} 232 233void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 234{ 235 struct drm_device *dev = crtc->dev; 236 struct radeon_device *rdev = dev->dev_private; 237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 238 239 switch (mode) { 240 case DRM_MODE_DPMS_ON: 241 radeon_crtc->enabled = true; 242 /* adjust pm to dpms changes BEFORE enabling crtcs */ 243 radeon_pm_compute_clocks(rdev); 244 atombios_enable_crtc(crtc, ATOM_ENABLE); 245 if (ASIC_IS_DCE3(rdev)) 246 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 247 atombios_blank_crtc(crtc, ATOM_DISABLE); 248 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 249 radeon_crtc_load_lut(crtc); 250 break; 251 case DRM_MODE_DPMS_STANDBY: 252 case DRM_MODE_DPMS_SUSPEND: 253 case DRM_MODE_DPMS_OFF: 254 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 255 if (radeon_crtc->enabled) 256 atombios_blank_crtc(crtc, ATOM_ENABLE); 257 if (ASIC_IS_DCE3(rdev)) 258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 259 atombios_enable_crtc(crtc, ATOM_DISABLE); 260 radeon_crtc->enabled = false; 261 /* adjust pm to dpms changes AFTER disabling crtcs */ 262 radeon_pm_compute_clocks(rdev); 263 break; 264 } 265} 266 267static void 268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 269 struct drm_display_mode *mode) 270{ 271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 272 struct drm_device *dev = crtc->dev; 273 struct radeon_device *rdev = dev->dev_private; 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 276 u16 misc = 0; 277 278 memset(&args, 0, sizeof(args)); 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 280 args.usH_Blanking_Time = 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 283 args.usV_Blanking_Time = 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 285 args.usH_SyncOffset = 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 287 args.usH_SyncWidth = 288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 289 args.usV_SyncOffset = 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 291 args.usV_SyncWidth = 292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 293 args.ucH_Border = radeon_crtc->h_border; 294 args.ucV_Border = radeon_crtc->v_border; 295 296 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 297 misc |= ATOM_VSYNC_POLARITY; 298 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 299 misc |= ATOM_HSYNC_POLARITY; 300 if (mode->flags & DRM_MODE_FLAG_CSYNC) 301 misc |= ATOM_COMPOSITESYNC; 302 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 303 misc |= ATOM_INTERLACE; 304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 305 misc |= ATOM_DOUBLE_CLOCK_MODE; 306 307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 308 args.ucCRTC = radeon_crtc->crtc_id; 309 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 311} 312 313static void atombios_crtc_set_timing(struct drm_crtc *crtc, 314 struct drm_display_mode *mode) 315{ 316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 317 struct drm_device *dev = crtc->dev; 318 struct radeon_device *rdev = dev->dev_private; 319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 321 u16 misc = 0; 322 323 memset(&args, 0, sizeof(args)); 324 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 327 args.usH_SyncWidth = 328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 332 args.usV_SyncWidth = 333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 334 335 args.ucOverscanRight = radeon_crtc->h_border; 336 args.ucOverscanLeft = radeon_crtc->h_border; 337 args.ucOverscanBottom = radeon_crtc->v_border; 338 args.ucOverscanTop = radeon_crtc->v_border; 339 340 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 341 misc |= ATOM_VSYNC_POLARITY; 342 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 343 misc |= ATOM_HSYNC_POLARITY; 344 if (mode->flags & DRM_MODE_FLAG_CSYNC) 345 misc |= ATOM_COMPOSITESYNC; 346 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 347 misc |= ATOM_INTERLACE; 348 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 349 misc |= ATOM_DOUBLE_CLOCK_MODE; 350 351 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 352 args.ucCRTC = radeon_crtc->crtc_id; 353 354 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 355} 356 357static void atombios_disable_ss(struct drm_crtc *crtc) 358{ 359 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 360 struct drm_device *dev = crtc->dev; 361 struct radeon_device *rdev = dev->dev_private; 362 u32 ss_cntl; 363 364 if (ASIC_IS_DCE4(rdev)) { 365 switch (radeon_crtc->pll_id) { 366 case ATOM_PPLL1: 367 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 368 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 369 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 370 break; 371 case ATOM_PPLL2: 372 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 373 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 374 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 375 break; 376 case ATOM_DCPLL: 377 case ATOM_PPLL_INVALID: 378 return; 379 } 380 } else if (ASIC_IS_AVIVO(rdev)) { 381 switch (radeon_crtc->pll_id) { 382 case ATOM_PPLL1: 383 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 384 ss_cntl &= ~1; 385 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 386 break; 387 case ATOM_PPLL2: 388 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 389 ss_cntl &= ~1; 390 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 391 break; 392 case ATOM_DCPLL: 393 case ATOM_PPLL_INVALID: 394 return; 395 } 396 } 397} 398 399 400union atom_enable_ss { 401 ENABLE_LVDS_SS_PARAMETERS legacy; 402 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 403}; 404 405static void atombios_enable_ss(struct drm_crtc *crtc) 406{ 407 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 408 struct drm_device *dev = crtc->dev; 409 struct radeon_device *rdev = dev->dev_private; 410 struct drm_encoder *encoder = NULL; 411 struct radeon_encoder *radeon_encoder = NULL; 412 struct radeon_encoder_atom_dig *dig = NULL; 413 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 414 union atom_enable_ss args; 415 uint16_t percentage = 0; 416 uint8_t type = 0, step = 0, delay = 0, range = 0; 417 418 if (ASIC_IS_DCE4(rdev)) 419 return; 420 421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 422 if (encoder->crtc == crtc) { 423 radeon_encoder = to_radeon_encoder(encoder); 424 /* only enable spread spectrum on LVDS */ 425 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 426 dig = radeon_encoder->enc_priv; 427 if (dig && dig->ss) { 428 percentage = dig->ss->percentage; 429 type = dig->ss->type; 430 step = dig->ss->step; 431 delay = dig->ss->delay; 432 range = dig->ss->range; 433 } else 434 return; 435 } else 436 return; 437 break; 438 } 439 } 440 441 if (!radeon_encoder) 442 return; 443 444 memset(&args, 0, sizeof(args)); 445 if (ASIC_IS_AVIVO(rdev)) { 446 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 447 args.v1.ucSpreadSpectrumType = type; 448 args.v1.ucSpreadSpectrumStep = step; 449 args.v1.ucSpreadSpectrumDelay = delay; 450 args.v1.ucSpreadSpectrumRange = range; 451 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 452 args.v1.ucEnable = ATOM_ENABLE; 453 } else { 454 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage); 455 args.legacy.ucSpreadSpectrumType = type; 456 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2; 457 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4; 458 args.legacy.ucEnable = ATOM_ENABLE; 459 } 460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 461} 462 463union adjust_pixel_clock { 464 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 465 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 466}; 467 468static u32 atombios_adjust_pll(struct drm_crtc *crtc, 469 struct drm_display_mode *mode, 470 struct radeon_pll *pll) 471{ 472 struct drm_device *dev = crtc->dev; 473 struct radeon_device *rdev = dev->dev_private; 474 struct drm_encoder *encoder = NULL; 475 struct radeon_encoder *radeon_encoder = NULL; 476 u32 adjusted_clock = mode->clock; 477 int encoder_mode = 0; 478 u32 dp_clock = mode->clock; 479 int bpc = 8; 480 481 /* reset the pll flags */ 482 pll->flags = 0; 483 484 /* select the PLL algo */ 485 if (ASIC_IS_AVIVO(rdev)) { 486 if (radeon_new_pll == 0) 487 pll->algo = PLL_ALGO_LEGACY; 488 else 489 pll->algo = PLL_ALGO_NEW; 490 } else { 491 if (radeon_new_pll == 1) 492 pll->algo = PLL_ALGO_NEW; 493 else 494 pll->algo = PLL_ALGO_LEGACY; 495 } 496 497 if (ASIC_IS_AVIVO(rdev)) { 498 if ((rdev->family == CHIP_RS600) || 499 (rdev->family == CHIP_RS690) || 500 (rdev->family == CHIP_RS740)) 501 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 502 RADEON_PLL_PREFER_CLOSEST_LOWER); 503 504 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 505 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 506 else 507 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 508 } else { 509 pll->flags |= RADEON_PLL_LEGACY; 510 511 if (mode->clock > 200000) /* range limits??? */ 512 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 513 else 514 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 515 516 } 517 518 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 519 if (encoder->crtc == crtc) { 520 radeon_encoder = to_radeon_encoder(encoder); 521 encoder_mode = atombios_get_encoder_mode(encoder); 522 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { 523 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 524 if (connector) { 525 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 526 struct radeon_connector_atom_dig *dig_connector = 527 radeon_connector->con_priv; 528 529 dp_clock = dig_connector->dp_clock; 530 } 531 } 532 533 if (ASIC_IS_AVIVO(rdev)) { 534 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 535 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 536 adjusted_clock = mode->clock * 2; 537 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 538 pll->algo = PLL_ALGO_LEGACY; 539 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 540 } 541 /* There is some evidence (often anecdotal) that RV515/RV620 LVDS 542 * (on some boards at least) prefers the legacy algo. I'm not 543 * sure whether this should handled generically or on a 544 * case-by-case quirk basis. Both algos should work fine in the 545 * majority of cases. 546 */ 547 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) && 548 ((rdev->family == CHIP_RV515) || 549 (rdev->family == CHIP_RV620))) { 550 /* allow the user to overrride just in case */ 551 if (radeon_new_pll == 1) 552 pll->algo = PLL_ALGO_NEW; 553 else 554 pll->algo = PLL_ALGO_LEGACY; 555 } 556 } else { 557 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 558 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 559 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 560 pll->flags |= RADEON_PLL_USE_REF_DIV; 561 } 562 break; 563 } 564 } 565 566 if (ASIC_IS_DCE3(rdev)) { 567 union adjust_pixel_clock args; 568 u8 frev, crev; 569 int index; 570 571 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 572 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 573 &crev)) 574 return adjusted_clock; 575 576 memset(&args, 0, sizeof(args)); 577 578 switch (frev) { 579 case 1: 580 switch (crev) { 581 case 1: 582 case 2: 583 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 584 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 585 args.v1.ucEncodeMode = encoder_mode; 586 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 587 /* may want to enable SS on DP eventually */ 588 /* args.v1.ucConfig |= 589 ADJUST_DISPLAY_CONFIG_SS_ENABLE;*/ 590 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) { 591 args.v1.ucConfig |= 592 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 593 } 594 595 atom_execute_table(rdev->mode_info.atom_context, 596 index, (uint32_t *)&args); 597 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 598 break; 599 case 3: 600 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 601 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 602 args.v3.sInput.ucEncodeMode = encoder_mode; 603 args.v3.sInput.ucDispPllConfig = 0; 604 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 605 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 606 607 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 608 /* may want to enable SS on DP/eDP eventually */ 609 /*args.v3.sInput.ucDispPllConfig |= 610 DISPPLL_CONFIG_SS_ENABLE;*/ 611 args.v3.sInput.ucDispPllConfig |= 612 DISPPLL_CONFIG_COHERENT_MODE; 613 /* 16200 or 27000 */ 614 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 615 } else { 616 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 617 /* deep color support */ 618 args.v3.sInput.usPixelClock = 619 cpu_to_le16((mode->clock * bpc / 8) / 10); 620 } 621 if (dig->coherent_mode) 622 args.v3.sInput.ucDispPllConfig |= 623 DISPPLL_CONFIG_COHERENT_MODE; 624 if (mode->clock > 165000) 625 args.v3.sInput.ucDispPllConfig |= 626 DISPPLL_CONFIG_DUAL_LINK; 627 } 628 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 629 if (encoder_mode == ATOM_ENCODER_MODE_DP) { 630 /* may want to enable SS on DP/eDP eventually */ 631 /*args.v3.sInput.ucDispPllConfig |= 632 DISPPLL_CONFIG_SS_ENABLE;*/ 633 args.v3.sInput.ucDispPllConfig |= 634 DISPPLL_CONFIG_COHERENT_MODE; 635 /* 16200 or 27000 */ 636 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 637 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) { 638 /* want to enable SS on LVDS eventually */ 639 /*args.v3.sInput.ucDispPllConfig |= 640 DISPPLL_CONFIG_SS_ENABLE;*/ 641 } else { 642 if (mode->clock > 165000) 643 args.v3.sInput.ucDispPllConfig |= 644 DISPPLL_CONFIG_DUAL_LINK; 645 } 646 } 647 atom_execute_table(rdev->mode_info.atom_context, 648 index, (uint32_t *)&args); 649 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 650 if (args.v3.sOutput.ucRefDiv) { 651 pll->flags |= RADEON_PLL_USE_REF_DIV; 652 pll->reference_div = args.v3.sOutput.ucRefDiv; 653 } 654 if (args.v3.sOutput.ucPostDiv) { 655 pll->flags |= RADEON_PLL_USE_POST_DIV; 656 pll->post_div = args.v3.sOutput.ucPostDiv; 657 } 658 break; 659 default: 660 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 661 return adjusted_clock; 662 } 663 break; 664 default: 665 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 666 return adjusted_clock; 667 } 668 } 669 return adjusted_clock; 670} 671 672union set_pixel_clock { 673 SET_PIXEL_CLOCK_PS_ALLOCATION base; 674 PIXEL_CLOCK_PARAMETERS v1; 675 PIXEL_CLOCK_PARAMETERS_V2 v2; 676 PIXEL_CLOCK_PARAMETERS_V3 v3; 677 PIXEL_CLOCK_PARAMETERS_V5 v5; 678}; 679 680static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) 681{ 682 struct drm_device *dev = crtc->dev; 683 struct radeon_device *rdev = dev->dev_private; 684 u8 frev, crev; 685 int index; 686 union set_pixel_clock args; 687 688 memset(&args, 0, sizeof(args)); 689 690 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 691 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 692 &crev)) 693 return; 694 695 switch (frev) { 696 case 1: 697 switch (crev) { 698 case 5: 699 /* if the default dcpll clock is specified, 700 * SetPixelClock provides the dividers 701 */ 702 args.v5.ucCRTC = ATOM_CRTC_INVALID; 703 args.v5.usPixelClock = rdev->clock.default_dispclk; 704 args.v5.ucPpll = ATOM_DCPLL; 705 break; 706 default: 707 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 708 return; 709 } 710 break; 711 default: 712 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 713 return; 714 } 715 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 716} 717 718static void atombios_crtc_program_pll(struct drm_crtc *crtc, 719 int crtc_id, 720 int pll_id, 721 u32 encoder_mode, 722 u32 encoder_id, 723 u32 clock, 724 u32 ref_div, 725 u32 fb_div, 726 u32 frac_fb_div, 727 u32 post_div) 728{ 729 struct drm_device *dev = crtc->dev; 730 struct radeon_device *rdev = dev->dev_private; 731 u8 frev, crev; 732 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 733 union set_pixel_clock args; 734 735 memset(&args, 0, sizeof(args)); 736 737 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 738 &crev)) 739 return; 740 741 switch (frev) { 742 case 1: 743 switch (crev) { 744 case 1: 745 if (clock == ATOM_DISABLE) 746 return; 747 args.v1.usPixelClock = cpu_to_le16(clock / 10); 748 args.v1.usRefDiv = cpu_to_le16(ref_div); 749 args.v1.usFbDiv = cpu_to_le16(fb_div); 750 args.v1.ucFracFbDiv = frac_fb_div; 751 args.v1.ucPostDiv = post_div; 752 args.v1.ucPpll = pll_id; 753 args.v1.ucCRTC = crtc_id; 754 args.v1.ucRefDivSrc = 1; 755 break; 756 case 2: 757 args.v2.usPixelClock = cpu_to_le16(clock / 10); 758 args.v2.usRefDiv = cpu_to_le16(ref_div); 759 args.v2.usFbDiv = cpu_to_le16(fb_div); 760 args.v2.ucFracFbDiv = frac_fb_div; 761 args.v2.ucPostDiv = post_div; 762 args.v2.ucPpll = pll_id; 763 args.v2.ucCRTC = crtc_id; 764 args.v2.ucRefDivSrc = 1; 765 break; 766 case 3: 767 args.v3.usPixelClock = cpu_to_le16(clock / 10); 768 args.v3.usRefDiv = cpu_to_le16(ref_div); 769 args.v3.usFbDiv = cpu_to_le16(fb_div); 770 args.v3.ucFracFbDiv = frac_fb_div; 771 args.v3.ucPostDiv = post_div; 772 args.v3.ucPpll = pll_id; 773 args.v3.ucMiscInfo = (pll_id << 2); 774 args.v3.ucTransmitterId = encoder_id; 775 args.v3.ucEncoderMode = encoder_mode; 776 break; 777 case 5: 778 args.v5.ucCRTC = crtc_id; 779 args.v5.usPixelClock = cpu_to_le16(clock / 10); 780 args.v5.ucRefDiv = ref_div; 781 args.v5.usFbDiv = cpu_to_le16(fb_div); 782 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 783 args.v5.ucPostDiv = post_div; 784 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 785 args.v5.ucTransmitterID = encoder_id; 786 args.v5.ucEncoderMode = encoder_mode; 787 args.v5.ucPpll = pll_id; 788 break; 789 default: 790 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 791 return; 792 } 793 break; 794 default: 795 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 796 return; 797 } 798 799 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 800} 801 802static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 803{ 804 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 805 struct drm_device *dev = crtc->dev; 806 struct radeon_device *rdev = dev->dev_private; 807 struct drm_encoder *encoder = NULL; 808 struct radeon_encoder *radeon_encoder = NULL; 809 u32 pll_clock = mode->clock; 810 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 811 struct radeon_pll *pll; 812 u32 adjusted_clock; 813 int encoder_mode = 0; 814 815 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 816 if (encoder->crtc == crtc) { 817 radeon_encoder = to_radeon_encoder(encoder); 818 encoder_mode = atombios_get_encoder_mode(encoder); 819 break; 820 } 821 } 822 823 if (!radeon_encoder) 824 return; 825 826 switch (radeon_crtc->pll_id) { 827 case ATOM_PPLL1: 828 pll = &rdev->clock.p1pll; 829 break; 830 case ATOM_PPLL2: 831 pll = &rdev->clock.p2pll; 832 break; 833 case ATOM_DCPLL: 834 case ATOM_PPLL_INVALID: 835 default: 836 pll = &rdev->clock.dcpll; 837 break; 838 } 839 840 /* adjust pixel clock as needed */ 841 adjusted_clock = atombios_adjust_pll(crtc, mode, pll); 842 843 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 844 &ref_div, &post_div); 845 846 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 847 encoder_mode, radeon_encoder->encoder_id, mode->clock, 848 ref_div, fb_div, frac_fb_div, post_div); 849 850} 851 852static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y, 853 struct drm_framebuffer *old_fb) 854{ 855 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 856 struct drm_device *dev = crtc->dev; 857 struct radeon_device *rdev = dev->dev_private; 858 struct radeon_framebuffer *radeon_fb; 859 struct drm_gem_object *obj; 860 struct radeon_bo *rbo; 861 uint64_t fb_location; 862 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 863 int r; 864 865 /* no fb bound */ 866 if (!crtc->fb) { 867 DRM_DEBUG_KMS("No FB bound\n"); 868 return 0; 869 } 870 871 radeon_fb = to_radeon_framebuffer(crtc->fb); 872 873 /* Pin framebuffer & get tilling informations */ 874 obj = radeon_fb->obj; 875 rbo = obj->driver_private; 876 r = radeon_bo_reserve(rbo, false); 877 if (unlikely(r != 0)) 878 return r; 879 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 880 if (unlikely(r != 0)) { 881 radeon_bo_unreserve(rbo); 882 return -EINVAL; 883 } 884 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 885 radeon_bo_unreserve(rbo); 886 887 switch (crtc->fb->bits_per_pixel) { 888 case 8: 889 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 890 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 891 break; 892 case 15: 893 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 894 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 895 break; 896 case 16: 897 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 898 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 899 break; 900 case 24: 901 case 32: 902 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 903 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 904 break; 905 default: 906 DRM_ERROR("Unsupported screen depth %d\n", 907 crtc->fb->bits_per_pixel); 908 return -EINVAL; 909 } 910 911 if (tiling_flags & RADEON_TILING_MACRO) 912 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 913 else if (tiling_flags & RADEON_TILING_MICRO) 914 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 915 916 switch (radeon_crtc->crtc_id) { 917 case 0: 918 WREG32(AVIVO_D1VGA_CONTROL, 0); 919 break; 920 case 1: 921 WREG32(AVIVO_D2VGA_CONTROL, 0); 922 break; 923 case 2: 924 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 925 break; 926 case 3: 927 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 928 break; 929 case 4: 930 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 931 break; 932 case 5: 933 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 934 break; 935 default: 936 break; 937 } 938 939 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 940 upper_32_bits(fb_location)); 941 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 942 upper_32_bits(fb_location)); 943 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 944 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 945 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 946 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 947 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 948 949 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 950 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 951 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 952 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 953 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); 954 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); 955 956 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 957 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 958 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 959 960 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 961 crtc->mode.vdisplay); 962 x &= ~3; 963 y &= ~1; 964 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 965 (x << 16) | y); 966 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 967 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 968 969 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 970 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 971 EVERGREEN_INTERLEAVE_EN); 972 else 973 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 974 975 if (old_fb && old_fb != crtc->fb) { 976 radeon_fb = to_radeon_framebuffer(old_fb); 977 rbo = radeon_fb->obj->driver_private; 978 r = radeon_bo_reserve(rbo, false); 979 if (unlikely(r != 0)) 980 return r; 981 radeon_bo_unpin(rbo); 982 radeon_bo_unreserve(rbo); 983 } 984 985 /* Bytes per pixel may have changed */ 986 radeon_bandwidth_update(rdev); 987 988 return 0; 989} 990 991static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y, 992 struct drm_framebuffer *old_fb) 993{ 994 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 995 struct drm_device *dev = crtc->dev; 996 struct radeon_device *rdev = dev->dev_private; 997 struct radeon_framebuffer *radeon_fb; 998 struct drm_gem_object *obj; 999 struct radeon_bo *rbo; 1000 uint64_t fb_location; 1001 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1002 int r; 1003 1004 /* no fb bound */ 1005 if (!crtc->fb) { 1006 DRM_DEBUG_KMS("No FB bound\n"); 1007 return 0; 1008 } 1009 1010 radeon_fb = to_radeon_framebuffer(crtc->fb); 1011 1012 /* Pin framebuffer & get tilling informations */ 1013 obj = radeon_fb->obj; 1014 rbo = obj->driver_private; 1015 r = radeon_bo_reserve(rbo, false); 1016 if (unlikely(r != 0)) 1017 return r; 1018 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1019 if (unlikely(r != 0)) { 1020 radeon_bo_unreserve(rbo); 1021 return -EINVAL; 1022 } 1023 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1024 radeon_bo_unreserve(rbo); 1025 1026 switch (crtc->fb->bits_per_pixel) { 1027 case 8: 1028 fb_format = 1029 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1030 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1031 break; 1032 case 15: 1033 fb_format = 1034 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1035 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1036 break; 1037 case 16: 1038 fb_format = 1039 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1040 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1041 break; 1042 case 24: 1043 case 32: 1044 fb_format = 1045 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1046 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1047 break; 1048 default: 1049 DRM_ERROR("Unsupported screen depth %d\n", 1050 crtc->fb->bits_per_pixel); 1051 return -EINVAL; 1052 } 1053 1054 if (rdev->family >= CHIP_R600) { 1055 if (tiling_flags & RADEON_TILING_MACRO) 1056 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1057 else if (tiling_flags & RADEON_TILING_MICRO) 1058 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1059 } else { 1060 if (tiling_flags & RADEON_TILING_MACRO) 1061 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1062 1063 if (tiling_flags & RADEON_TILING_MICRO) 1064 fb_format |= AVIVO_D1GRPH_TILED; 1065 } 1066 1067 if (radeon_crtc->crtc_id == 0) 1068 WREG32(AVIVO_D1VGA_CONTROL, 0); 1069 else 1070 WREG32(AVIVO_D2VGA_CONTROL, 0); 1071 1072 if (rdev->family >= CHIP_RV770) { 1073 if (radeon_crtc->crtc_id) { 1074 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1075 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1076 } else { 1077 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1078 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1079 } 1080 } 1081 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1082 (u32) fb_location); 1083 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1084 radeon_crtc->crtc_offset, (u32) fb_location); 1085 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1086 1087 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1088 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1089 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1090 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1091 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); 1092 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); 1093 1094 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); 1095 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1096 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1097 1098 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1099 crtc->mode.vdisplay); 1100 x &= ~3; 1101 y &= ~1; 1102 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1103 (x << 16) | y); 1104 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1105 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1106 1107 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) 1108 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1109 AVIVO_D1MODE_INTERLEAVE_EN); 1110 else 1111 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1112 1113 if (old_fb && old_fb != crtc->fb) { 1114 radeon_fb = to_radeon_framebuffer(old_fb); 1115 rbo = radeon_fb->obj->driver_private; 1116 r = radeon_bo_reserve(rbo, false); 1117 if (unlikely(r != 0)) 1118 return r; 1119 radeon_bo_unpin(rbo); 1120 radeon_bo_unreserve(rbo); 1121 } 1122 1123 /* Bytes per pixel may have changed */ 1124 radeon_bandwidth_update(rdev); 1125 1126 return 0; 1127} 1128 1129int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1130 struct drm_framebuffer *old_fb) 1131{ 1132 struct drm_device *dev = crtc->dev; 1133 struct radeon_device *rdev = dev->dev_private; 1134 1135 if (ASIC_IS_DCE4(rdev)) 1136 return evergreen_crtc_set_base(crtc, x, y, old_fb); 1137 else if (ASIC_IS_AVIVO(rdev)) 1138 return avivo_crtc_set_base(crtc, x, y, old_fb); 1139 else 1140 return radeon_crtc_set_base(crtc, x, y, old_fb); 1141} 1142 1143/* properly set additional regs when using atombios */ 1144static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1145{ 1146 struct drm_device *dev = crtc->dev; 1147 struct radeon_device *rdev = dev->dev_private; 1148 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1149 u32 disp_merge_cntl; 1150 1151 switch (radeon_crtc->crtc_id) { 1152 case 0: 1153 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1154 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1155 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1156 break; 1157 case 1: 1158 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1159 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1160 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1161 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1162 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1163 break; 1164 } 1165} 1166 1167static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1168{ 1169 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1170 struct drm_device *dev = crtc->dev; 1171 struct radeon_device *rdev = dev->dev_private; 1172 struct drm_encoder *test_encoder; 1173 struct drm_crtc *test_crtc; 1174 uint32_t pll_in_use = 0; 1175 1176 if (ASIC_IS_DCE4(rdev)) { 1177 /* if crtc is driving DP and we have an ext clock, use that */ 1178 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1179 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1180 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { 1181 if (rdev->clock.dp_extclk) 1182 return ATOM_PPLL_INVALID; 1183 } 1184 } 1185 } 1186 1187 /* otherwise, pick one of the plls */ 1188 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1189 struct radeon_crtc *radeon_test_crtc; 1190 1191 if (crtc == test_crtc) 1192 continue; 1193 1194 radeon_test_crtc = to_radeon_crtc(test_crtc); 1195 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && 1196 (radeon_test_crtc->pll_id <= ATOM_PPLL2)) 1197 pll_in_use |= (1 << radeon_test_crtc->pll_id); 1198 } 1199 if (!(pll_in_use & 1)) 1200 return ATOM_PPLL1; 1201 return ATOM_PPLL2; 1202 } else 1203 return radeon_crtc->crtc_id; 1204 1205} 1206 1207int atombios_crtc_mode_set(struct drm_crtc *crtc, 1208 struct drm_display_mode *mode, 1209 struct drm_display_mode *adjusted_mode, 1210 int x, int y, struct drm_framebuffer *old_fb) 1211{ 1212 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1213 struct drm_device *dev = crtc->dev; 1214 struct radeon_device *rdev = dev->dev_private; 1215 struct drm_encoder *encoder; 1216 bool is_tvcv = false; 1217 1218 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1219 /* find tv std */ 1220 if (encoder->crtc == crtc) { 1221 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1222 if (radeon_encoder->active_device & 1223 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1224 is_tvcv = true; 1225 } 1226 } 1227 1228 atombios_disable_ss(crtc); 1229 /* always set DCPLL */ 1230 if (ASIC_IS_DCE4(rdev)) 1231 atombios_crtc_set_dcpll(crtc); 1232 atombios_crtc_set_pll(crtc, adjusted_mode); 1233 atombios_enable_ss(crtc); 1234 1235 if (ASIC_IS_DCE4(rdev)) 1236 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1237 else if (ASIC_IS_AVIVO(rdev)) { 1238 if (is_tvcv) 1239 atombios_crtc_set_timing(crtc, adjusted_mode); 1240 else 1241 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1242 } else { 1243 atombios_crtc_set_timing(crtc, adjusted_mode); 1244 if (radeon_crtc->crtc_id == 0) 1245 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1246 radeon_legacy_atom_fixup(crtc); 1247 } 1248 atombios_crtc_set_base(crtc, x, y, old_fb); 1249 atombios_overscan_setup(crtc, mode, adjusted_mode); 1250 atombios_scaler_setup(crtc); 1251 return 0; 1252} 1253 1254static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1255 struct drm_display_mode *mode, 1256 struct drm_display_mode *adjusted_mode) 1257{ 1258 struct drm_device *dev = crtc->dev; 1259 struct radeon_device *rdev = dev->dev_private; 1260 1261 /* adjust pm to upcoming mode change */ 1262 radeon_pm_compute_clocks(rdev); 1263 1264 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1265 return false; 1266 return true; 1267} 1268 1269static void atombios_crtc_prepare(struct drm_crtc *crtc) 1270{ 1271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1272 1273 /* pick pll */ 1274 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1275 1276 atombios_lock_crtc(crtc, ATOM_ENABLE); 1277 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1278} 1279 1280static void atombios_crtc_commit(struct drm_crtc *crtc) 1281{ 1282 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1283 atombios_lock_crtc(crtc, ATOM_DISABLE); 1284} 1285 1286static void atombios_crtc_disable(struct drm_crtc *crtc) 1287{ 1288 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1289 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1290 1291 switch (radeon_crtc->pll_id) { 1292 case ATOM_PPLL1: 1293 case ATOM_PPLL2: 1294 /* disable the ppll */ 1295 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1296 0, 0, ATOM_DISABLE, 0, 0, 0, 0); 1297 break; 1298 default: 1299 break; 1300 } 1301 radeon_crtc->pll_id = -1; 1302} 1303 1304static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1305 .dpms = atombios_crtc_dpms, 1306 .mode_fixup = atombios_crtc_mode_fixup, 1307 .mode_set = atombios_crtc_mode_set, 1308 .mode_set_base = atombios_crtc_set_base, 1309 .prepare = atombios_crtc_prepare, 1310 .commit = atombios_crtc_commit, 1311 .load_lut = radeon_crtc_load_lut, 1312 .disable = atombios_crtc_disable, 1313}; 1314 1315void radeon_atombios_init_crtc(struct drm_device *dev, 1316 struct radeon_crtc *radeon_crtc) 1317{ 1318 struct radeon_device *rdev = dev->dev_private; 1319 1320 if (ASIC_IS_DCE4(rdev)) { 1321 switch (radeon_crtc->crtc_id) { 1322 case 0: 1323 default: 1324 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1325 break; 1326 case 1: 1327 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1328 break; 1329 case 2: 1330 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1331 break; 1332 case 3: 1333 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1334 break; 1335 case 4: 1336 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1337 break; 1338 case 5: 1339 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1340 break; 1341 } 1342 } else { 1343 if (radeon_crtc->crtc_id == 1) 1344 radeon_crtc->crtc_offset = 1345 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1346 else 1347 radeon_crtc->crtc_offset = 0; 1348 } 1349 radeon_crtc->pll_id = -1; 1350 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1351} 1352