Searched refs:xa (Results 251 - 275 of 1008) sorted by relevance

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/netbsd-current/sys/dev/vme/
H A Dxd.c498 struct xdc_attach_args xa; local
671 xa.fullmode = XD_SUB_POLL;
672 xa.booting = 1;
674 for (xa.driveno = 0; xa.driveno < XDC_MAXDEV; xa.driveno++)
675 (void) config_found(self, (void *) &xa, NULL, CFARGS_NONE);
692 struct xdc_attach_args *xa = aux; local
697 cf->cf_loc[XDCCF_DRIVE] != xa->driveno)
713 struct xdc_attach_args *xa local
1137 struct xdc_attach_args xa; local
1235 struct xdc_attach_args xa; local
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_sh_mask.h74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
292 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
368 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
433 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
503 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
560 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
H A Dsdma0_4_2_sh_mask.h74 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
292 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
362 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
427 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
497 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
554 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_sh_mask.h230 #define RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
281 #define RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
327 #define RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
939 #define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
1033 #define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
1184 #define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
1349 #define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
1505 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
1578 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
1935 #define BIF_BX_PF_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_2_2_sh_mask.h74 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
292 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
H A Dsdma1_4_2_sh_mask.h74 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
172 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
229 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
294 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
360 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
419 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
489 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
546 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma2/
H A Dsdma2_4_2_2_sh_mask.h74 #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA2_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT 0xa
292 #define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_sh_mask.h74 #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA3_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT 0xa
292 #define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma4/
H A Dsdma4_4_2_2_sh_mask.h74 #define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA4_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA4_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL__SHIFT 0xa
292 #define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA4_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma5/
H A Dsdma5_4_2_2_sh_mask.h74 #define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA5_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA5_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL__SHIFT 0xa
292 #define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA5_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA5_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA5_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma6/
H A Dsdma6_4_2_2_sh_mask.h74 #define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA6_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA6_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL__SHIFT 0xa
292 #define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA6_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA6_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA6_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma7/
H A Dsdma7_4_2_2_sh_mask.h74 #define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA7_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA7_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL__SHIFT 0xa
292 #define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT__SHIFT 0xa
364 #define SDMA7_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
423 #define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
493 #define SDMA7_STATUS_REG__EX_IDLE__SHIFT 0xa
550 #define SDMA7_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h102 #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
140 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
152 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
236 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
328 #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
364 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
408 #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
438 #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
546 #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
568 #define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa
[all...]
H A Doss_3_0_sh_mask.h100 #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
136 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
146 #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0xa
230 #define IH_RESET_INCOMPLETE_INT_CNTL__SDMA0__SHIFT 0xa
276 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__SDMA0__SHIFT 0xa
356 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
450 #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
488 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
532 #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
562 #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_1_0_sh_mask.h65 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
140 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
173 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa
301 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa
321 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa
441 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa
578 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa
624 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa
747 #define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
821 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h146 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
186 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
290 #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
404 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
422 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
452 #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
552 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
594 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
708 #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
732 #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
[all...]
/netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/pkcs7/
H A Dpk7_doit.c200 X509_ALGOR *xa = NULL; local
255 xa = p7->d.digest->md;
269 if (xa && !PKCS7_bio_add_digest(&out, xa))
363 X509_ALGOR *xa; local
443 xa = sk_X509_ALGOR_value(md_sk, i);
449 j = OBJ_obj2nid(xa->algorithm);
1084 X509_ATTRIBUTE *xa; local
1086 xa = X509at_get_attr(sk, idx);
1087 return X509_ATTRIBUTE_get0_type(xa,
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h58 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
118 #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa
170 #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa
250 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
274 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa
298 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa
330 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa
420 #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
444 #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
544 #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/athub/
H A Dathub_2_0_0_sh_mask.h56 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
63 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
95 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa
182 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
359 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
787 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa
820 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa
1073 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
1084 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
1095 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_enum.h75 BLEND_SRC_ALPHA_SATURATE = 0xa,
115 CMASK_CLR10_F2 = 0xa,
138 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
597 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
648 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
670 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
771 STENCIL_AND = 0xa,
801 DB_PERF_SEL_DB_SC_tile_sends = 0xa,
1097 GRBM_PERF_SEL_RESERVED_6 = 0xa,
1133 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
[all...]
H A Dgfx_8_0_enum.h75 BLEND_SRC_ALPHA_SATURATE = 0xa,
115 CMASK_CLR10_F2 = 0xa,
138 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
588 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
639 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
661 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
762 STENCIL_AND = 0xa,
792 DB_PERF_SEL_DB_SC_tile_sends = 0xa,
1079 GRBM_PERF_SEL_RESERVED_6 = 0xa,
1115 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
[all...]
H A Dgfx_7_2_enum.h74 BLEND_SRC_ALPHA_SATURATE = 0xa,
114 CMASK_CLR10_F2 = 0xa,
132 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa,
412 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa,
460 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa,
479 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa,
577 STENCIL_AND = 0xa,
607 DB_PERF_SEL_DB_SC_tile_sends = 0xa,
894 GRBM_PERF_SEL_RESERVED_6 = 0xa,
930 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa,
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.mi/
H A Dmi2-amd64-entry-value.s339 .uleb128 0xa # (DIE (0xf5) DW_TAG_GNU_call_site_parameter)
345 .uleb128 0xa # (DIE (0xfb) DW_TAG_GNU_call_site_parameter)
383 .uleb128 0xa # (DIE (0x157) DW_TAG_GNU_call_site_parameter)
388 .uleb128 0xa # (DIE (0x15c) DW_TAG_GNU_call_site_parameter)
420 .uleb128 0xa # (DIE (0x1a9) DW_TAG_GNU_call_site_parameter)
425 .uleb128 0xa # (DIE (0x1ae) DW_TAG_GNU_call_site_parameter)
453 .uleb128 0xa # (DIE (0x1f4) DW_TAG_GNU_call_site_parameter)
466 .uleb128 0xa # (DIE (0x218) DW_TAG_GNU_call_site_parameter)
551 .uleb128 0xa # (DW_FORM_block1)
570 .uleb128 0xa # (DW_FORM_block
[all...]
/netbsd-current/external/gpl3/gdb/dist/gdb/testsuite/gdb.mi/
H A Dmi2-amd64-entry-value.s339 .uleb128 0xa # (DIE (0xf5) DW_TAG_GNU_call_site_parameter)
345 .uleb128 0xa # (DIE (0xfb) DW_TAG_GNU_call_site_parameter)
383 .uleb128 0xa # (DIE (0x157) DW_TAG_GNU_call_site_parameter)
388 .uleb128 0xa # (DIE (0x15c) DW_TAG_GNU_call_site_parameter)
420 .uleb128 0xa # (DIE (0x1a9) DW_TAG_GNU_call_site_parameter)
425 .uleb128 0xa # (DIE (0x1ae) DW_TAG_GNU_call_site_parameter)
453 .uleb128 0xa # (DIE (0x1f4) DW_TAG_GNU_call_site_parameter)
466 .uleb128 0xa # (DIE (0x218) DW_TAG_GNU_call_site_parameter)
551 .uleb128 0xa # (DW_FORM_block1)
570 .uleb128 0xa # (DW_FORM_block
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_2_sh_mask.h82 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
112 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
158 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
206 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
360 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
440 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
518 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
558 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
604 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
630 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
[all...]

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