189857Sobrien/* $NetBSD: oss_2_4_sh_mask.h,v 1.3 2021/12/18 23:45:21 riastradh Exp $ */ 280016Sobrien 389857Sobrien/* 489857Sobrien * OSS_2_4 Register documentation 580016Sobrien * 689857Sobrien * Copyright (C) 2014 Advanced Micro Devices, Inc. 778828Sobrien * 889857Sobrien * Permission is hereby granted, free of charge, to any person obtaining a 989857Sobrien * copy of this software and associated documentation files (the "Software"), 1078828Sobrien * to deal in the Software without restriction, including without limitation 1189857Sobrien * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1278828Sobrien * and/or sell copies of the Software, and to permit persons to whom the 1389857Sobrien * Software is furnished to do so, subject to the following conditions: 1489857Sobrien * 1589857Sobrien * The above copyright notice and this permission notice shall be included 1689857Sobrien * in all copies or substantial portions of the Software. 1789857Sobrien * 1889857Sobrien * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1989857Sobrien * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2089857Sobrien * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2189857Sobrien * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 2289857Sobrien * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2389857Sobrien * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2489857Sobrien */ 2589857Sobrien 2689857Sobrien#ifndef OSS_2_4_SH_MASK_H 2789857Sobrien#define OSS_2_4_SH_MASK_H 2889857Sobrien 2989857Sobrien#define IH_VMID_0_LUT__PASID_MASK 0xffff 3089857Sobrien#define IH_VMID_0_LUT__PASID__SHIFT 0x0 3189857Sobrien#define IH_VMID_1_LUT__PASID_MASK 0xffff 3289857Sobrien#define IH_VMID_1_LUT__PASID__SHIFT 0x0 3389857Sobrien#define IH_VMID_2_LUT__PASID_MASK 0xffff 3489857Sobrien#define IH_VMID_2_LUT__PASID__SHIFT 0x0 3589857Sobrien#define IH_VMID_3_LUT__PASID_MASK 0xffff 3689857Sobrien#define IH_VMID_3_LUT__PASID__SHIFT 0x0 3789857Sobrien#define IH_VMID_4_LUT__PASID_MASK 0xffff 3889857Sobrien#define IH_VMID_4_LUT__PASID__SHIFT 0x0 3989857Sobrien#define IH_VMID_5_LUT__PASID_MASK 0xffff 4089857Sobrien#define IH_VMID_5_LUT__PASID__SHIFT 0x0 4189857Sobrien#define IH_VMID_6_LUT__PASID_MASK 0xffff 4289857Sobrien#define IH_VMID_6_LUT__PASID__SHIFT 0x0 4389857Sobrien#define IH_VMID_7_LUT__PASID_MASK 0xffff 4489857Sobrien#define IH_VMID_7_LUT__PASID__SHIFT 0x0 4589857Sobrien#define IH_VMID_8_LUT__PASID_MASK 0xffff 4689857Sobrien#define IH_VMID_8_LUT__PASID__SHIFT 0x0 4789857Sobrien#define IH_VMID_9_LUT__PASID_MASK 0xffff 4889857Sobrien#define IH_VMID_9_LUT__PASID__SHIFT 0x0 4989857Sobrien#define IH_VMID_10_LUT__PASID_MASK 0xffff 5089857Sobrien#define IH_VMID_10_LUT__PASID__SHIFT 0x0 5189857Sobrien#define IH_VMID_11_LUT__PASID_MASK 0xffff 5289857Sobrien#define IH_VMID_11_LUT__PASID__SHIFT 0x0 5389857Sobrien#define IH_VMID_12_LUT__PASID_MASK 0xffff 5489857Sobrien#define IH_VMID_12_LUT__PASID__SHIFT 0x0 5589857Sobrien#define IH_VMID_13_LUT__PASID_MASK 0xffff 5689857Sobrien#define IH_VMID_13_LUT__PASID__SHIFT 0x0 5789857Sobrien#define IH_VMID_14_LUT__PASID_MASK 0xffff 5889857Sobrien#define IH_VMID_14_LUT__PASID__SHIFT 0x0 5989857Sobrien#define IH_VMID_15_LUT__PASID_MASK 0xffff 6089857Sobrien#define IH_VMID_15_LUT__PASID__SHIFT 0x0 6189857Sobrien#define IH_RB_CNTL__RB_ENABLE_MASK 0x1 6289857Sobrien#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 6389857Sobrien#define IH_RB_CNTL__RB_SIZE_MASK 0x3e 6489857Sobrien#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 6589857Sobrien#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x40 6689857Sobrien#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x6 6789857Sobrien#define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x80 6889857Sobrien#define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 6989857Sobrien#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x100 7089857Sobrien#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 7189857Sobrien#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x3e00 7289857Sobrien#define IH_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 7389857Sobrien#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x10000 7489857Sobrien#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 7589857Sobrien#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000 7689857Sobrien#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 7789857Sobrien#define IH_RB_BASE__ADDR_MASK 0xffffffff 7889857Sobrien#define IH_RB_BASE__ADDR__SHIFT 0x0 7989857Sobrien#define IH_RB_RPTR__OFFSET_MASK 0x3fffc 8089857Sobrien#define IH_RB_RPTR__OFFSET__SHIFT 0x2 8189857Sobrien#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1 8289857Sobrien#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 8389857Sobrien#define IH_RB_WPTR__OFFSET_MASK 0x3fffc 8489857Sobrien#define IH_RB_WPTR__OFFSET__SHIFT 0x2 8589857Sobrien#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x40000 8689857Sobrien#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 8789857Sobrien#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x80000 8889857Sobrien#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 8989857Sobrien#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0xff 9089857Sobrien#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 9189857Sobrien#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xfffffffc 9289857Sobrien#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 9389857Sobrien#define IH_CNTL__ENABLE_INTR_MASK 0x1 9489857Sobrien#define IH_CNTL__ENABLE_INTR__SHIFT 0x0 9589857Sobrien#define IH_CNTL__MC_SWAP_MASK 0x6 9689857Sobrien#define IH_CNTL__MC_SWAP__SHIFT 0x1 9789857Sobrien#define IH_CNTL__RPTR_REARM_MASK 0x10 9889857Sobrien#define IH_CNTL__RPTR_REARM__SHIFT 0x4 9989857Sobrien#define IH_CNTL__CLIENT_FIFO_HIGHWATER_MASK 0x300 10089857Sobrien#define IH_CNTL__CLIENT_FIFO_HIGHWATER__SHIFT 0x8 10189857Sobrien#define IH_CNTL__MC_FIFO_HIGHWATER_MASK 0x7c00 10289857Sobrien#define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa 10389857Sobrien#define IH_CNTL__MC_WRREQ_CREDIT_MASK 0xf8000 10489857Sobrien#define IH_CNTL__MC_WRREQ_CREDIT__SHIFT 0xf 10589857Sobrien#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x1f00000 10689857Sobrien#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 10789857Sobrien#define IH_CNTL__MC_VMID_MASK 0x1e000000 10889857Sobrien#define IH_CNTL__MC_VMID__SHIFT 0x19 10989857Sobrien#define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1 11089857Sobrien#define IH_LEVEL_STATUS__DC_STATUS__SHIFT 0x0 11189857Sobrien#define IH_LEVEL_STATUS__ROM_STATUS_MASK 0x4 11289857Sobrien#define IH_LEVEL_STATUS__ROM_STATUS__SHIFT 0x2 11389857Sobrien#define IH_LEVEL_STATUS__SRBM_STATUS_MASK 0x8 11489857Sobrien#define IH_LEVEL_STATUS__SRBM_STATUS__SHIFT 0x3 11589857Sobrien#define IH_LEVEL_STATUS__BIF_STATUS_MASK 0x10 11689857Sobrien#define IH_LEVEL_STATUS__BIF_STATUS__SHIFT 0x4 11789857Sobrien#define IH_LEVEL_STATUS__XDMA_STATUS_MASK 0x20 11889857Sobrien#define IH_LEVEL_STATUS__XDMA_STATUS__SHIFT 0x5 11989857Sobrien#define IH_STATUS__IDLE_MASK 0x1 12089857Sobrien#define IH_STATUS__IDLE__SHIFT 0x0 12189857Sobrien#define IH_STATUS__INPUT_IDLE_MASK 0x2 12289857Sobrien#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 12389857Sobrien#define IH_STATUS__RB_IDLE_MASK 0x4 12489857Sobrien#define IH_STATUS__RB_IDLE__SHIFT 0x2 12589857Sobrien#define IH_STATUS__RB_FULL_MASK 0x8 12689857Sobrien#define IH_STATUS__RB_FULL__SHIFT 0x3 12789857Sobrien#define IH_STATUS__RB_FULL_DRAIN_MASK 0x10 12889857Sobrien#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 12989857Sobrien#define IH_STATUS__RB_OVERFLOW_MASK 0x20 13089857Sobrien#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 13189857Sobrien#define IH_STATUS__MC_WR_IDLE_MASK 0x40 13289857Sobrien#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 13389857Sobrien#define IH_STATUS__MC_WR_STALL_MASK 0x80 13489857Sobrien#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 13589857Sobrien#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x100 13689857Sobrien#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 13789857Sobrien#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x200 13889857Sobrien#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 13989857Sobrien#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x400 14089857Sobrien#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 14189857Sobrien#define IH_PERFMON_CNTL__ENABLE0_MASK 0x1 14289857Sobrien#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 14389857Sobrien#define IH_PERFMON_CNTL__CLEAR0_MASK 0x2 14489857Sobrien#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 14589857Sobrien#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 14689857Sobrien#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 14789857Sobrien#define IH_PERFMON_CNTL__ENABLE1_MASK 0x100 14889857Sobrien#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x8 14989857Sobrien#define IH_PERFMON_CNTL__CLEAR1_MASK 0x200 15089857Sobrien#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x9 15189857Sobrien#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 15289857Sobrien#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 15389857Sobrien#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 15489857Sobrien#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 15589857Sobrien#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 15689857Sobrien#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 15789857Sobrien#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xffffffff 15889857Sobrien#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 15989857Sobrien#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xffffffff 16089857Sobrien#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 16189857Sobrien#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xffffffff 16289857Sobrien#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 16389857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1 16489857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 16589857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x4 16689857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 16789857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x8 16889857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 16989857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x10 17089857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 17189857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x20 17289857Sobrien#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 17389857Sobrien#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0xfffffff 17489857Sobrien#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 17589857Sobrien#define IH_VERSION__VALUE_MASK 0xfff 17689857Sobrien#define IH_VERSION__VALUE__SHIFT 0x0 17789857Sobrien#define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x3 17889857Sobrien#define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 17989857Sobrien#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0xfc 18089857Sobrien#define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 18189857Sobrien#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x3f00 18289857Sobrien#define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 18389857Sobrien#define SDMA_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 18489857Sobrien#define SDMA_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 18589857Sobrien#define SDMA_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 18689857Sobrien#define SDMA_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 18789857Sobrien#define SDMA1_CONFIG__SDMA_RDREQ_URG_MASK 0xf00 18889857Sobrien#define SDMA1_CONFIG__SDMA_RDREQ_URG__SHIFT 0x8 18989857Sobrien#define SDMA1_CONFIG__SDMA_REQ_TRAN_MASK 0x10000 19089857Sobrien#define SDMA1_CONFIG__SDMA_REQ_TRAN__SHIFT 0x10 19189857Sobrien#define UVD_CONFIG__UVD_RDREQ_URG_MASK 0xf00 19289857Sobrien#define UVD_CONFIG__UVD_RDREQ_URG__SHIFT 0x8 19389857Sobrien#define UVD_CONFIG__UVD_REQ_TRAN_MASK 0x10000 19489857Sobrien#define UVD_CONFIG__UVD_REQ_TRAN__SHIFT 0x10 19589857Sobrien#define VCE_CONFIG__VCE_RDREQ_URG_MASK 0xf00 19689857Sobrien#define VCE_CONFIG__VCE_RDREQ_URG__SHIFT 0x8 19789857Sobrien#define VCE_CONFIG__VCE_REQ_TRAN_MASK 0x10000 19889857Sobrien#define VCE_CONFIG__VCE_REQ_TRAN__SHIFT 0x10 19989857Sobrien#define ACP_CONFIG__ACP_RDREQ_URG_MASK 0xf00 20078828Sobrien#define ACP_CONFIG__ACP_RDREQ_URG__SHIFT 0x8 20178828Sobrien#define ACP_CONFIG__ACP_REQ_TRAN_MASK 0x10000 20278828Sobrien#define ACP_CONFIG__ACP_REQ_TRAN__SHIFT 0x10 20389857Sobrien#define CPG_CONFIG__CPG_RDREQ_URG_MASK 0xf00 20489857Sobrien#define CPG_CONFIG__CPG_RDREQ_URG__SHIFT 0x8 20589857Sobrien#define CPG_CONFIG__CPG_REQ_TRAN_MASK 0x10000 20689857Sobrien#define CPG_CONFIG__CPG_REQ_TRAN__SHIFT 0x10 20789857Sobrien#define CPC1_CONFIG__CPC1_RDREQ_URG_MASK 0xf00 20889857Sobrien#define CPC1_CONFIG__CPC1_RDREQ_URG__SHIFT 0x8 20989857Sobrien#define CPC1_CONFIG__CPC1_REQ_TRAN_MASK 0x10000 21089857Sobrien#define CPC1_CONFIG__CPC1_REQ_TRAN__SHIFT 0x10 21189857Sobrien#define CPC2_CONFIG__CPC2_RDREQ_URG_MASK 0xf00 21289857Sobrien#define CPC2_CONFIG__CPC2_RDREQ_URG__SHIFT 0x8 21389857Sobrien#define CPC2_CONFIG__CPC2_REQ_TRAN_MASK 0x10000 21489857Sobrien#define CPC2_CONFIG__CPC2_REQ_TRAN__SHIFT 0x10 21589857Sobrien#define SEM_STATUS__SEM_IDLE_MASK 0x1 21689857Sobrien#define SEM_STATUS__SEM_IDLE__SHIFT 0x0 21789857Sobrien#define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x2 21889857Sobrien#define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 21989857Sobrien#define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x4 22089857Sobrien#define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 22189857Sobrien#define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x8 22289857Sobrien#define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 22389857Sobrien#define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x10 22489857Sobrien#define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 22589857Sobrien#define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x20 22689857Sobrien#define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 22789857Sobrien#define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x40 22889857Sobrien#define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 22989857Sobrien#define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x80 23089857Sobrien#define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 23189857Sobrien#define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x100 23289857Sobrien#define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 23389857Sobrien#define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x200 23489857Sobrien#define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 23589857Sobrien#define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x400 23689857Sobrien#define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 23789857Sobrien#define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x800 23889857Sobrien#define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 23989857Sobrien#define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x1000 24089857Sobrien#define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 24189857Sobrien#define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x2000 24289857Sobrien#define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 24389857Sobrien#define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x4000 24489857Sobrien#define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 24589857Sobrien#define SEM_EDC_CONFIG__DIS_EDC_MASK 0x2 24689857Sobrien#define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 24789857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x7 24889857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 24989857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x38 25089857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 25189857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x1c0 25289857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 25389857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0xe00 25489857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 25589857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x7000 25689857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 25789857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x38000 25889857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 25989857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x1c0000 26089857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 26189857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0xe00000 26289857Sobrien#define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 26389857Sobrien#define SEM_MAILBOX__SIDEPORT_MASK 0xff 26489857Sobrien#define SEM_MAILBOX__SIDEPORT__SHIFT 0x0 26589857Sobrien#define SEM_MAILBOX__HOSTPORT_MASK 0xff00 26689857Sobrien#define SEM_MAILBOX__HOSTPORT__SHIFT 0x8 26789857Sobrien#define SEM_MAILBOX__SIDEPORT_EXTRA_MASK 0xff0000 26889857Sobrien#define SEM_MAILBOX__SIDEPORT_EXTRA__SHIFT 0x10 26989857Sobrien#define SEM_MAILBOX__HOSTPORT_EXTRA_MASK 0xff000000 27089857Sobrien#define SEM_MAILBOX__HOSTPORT_EXTRA__SHIFT 0x18 27189857Sobrien#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_MASK 0xff 27289857Sobrien#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE__SHIFT 0x0 27389857Sobrien#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0xff00 27489857Sobrien#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x8 27577298Sobrien#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA_MASK 0xff0000 27668765Sobrien#define SEM_MAILBOX_CONTROL__SIDEPORT_ENABLE_EXTRA__SHIFT 0x10 27777298Sobrien#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA_MASK 0xff000000 27868765Sobrien#define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_EXTRA__SHIFT 0x18 27977298Sobrien#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1 28077298Sobrien#define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 28177298Sobrien#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x2 28277298Sobrien#define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 28377298Sobrien#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x4 28477298Sobrien#define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 28577298Sobrien#define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x18 28677298Sobrien#define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 28777298Sobrien#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0xf00 28877298Sobrien#define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 28977298Sobrien#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x1f 29077298Sobrien#define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 29177298Sobrien#define SRBM_CNTL__PWR_REQUEST_HALT_MASK 0x10000 29277298Sobrien#define SRBM_CNTL__PWR_REQUEST_HALT__SHIFT 0x10 29377298Sobrien#define SRBM_CNTL__COMBINE_SYSTEM_MC_MASK 0x20000 29477298Sobrien#define SRBM_CNTL__COMBINE_SYSTEM_MC__SHIFT 0x11 29577298Sobrien#define SRBM_CNTL__REPORT_LAST_RDERR_MASK 0x40000 29677298Sobrien#define SRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x12 29777298Sobrien#define SRBM_GFX_CNTL__PIPEID_MASK 0x3 29877298Sobrien#define SRBM_GFX_CNTL__PIPEID__SHIFT 0x0 29977298Sobrien#define SRBM_GFX_CNTL__MEID_MASK 0xc 30077298Sobrien#define SRBM_GFX_CNTL__MEID__SHIFT 0x2 30177298Sobrien#define SRBM_GFX_CNTL__VMID_MASK 0xf0 30277298Sobrien#define SRBM_GFX_CNTL__VMID__SHIFT 0x4 30377298Sobrien#define SRBM_GFX_CNTL__QUEUEID_MASK 0x700 30477298Sobrien#define SRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 30577298Sobrien#define SRBM_READ_CNTL__READ_TIMEOUT_MASK 0xffffff 30677298Sobrien#define SRBM_READ_CNTL__READ_TIMEOUT__SHIFT 0x0 30777298Sobrien#define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1 30877298Sobrien#define SRBM_STATUS2__SDMA_RQ_PENDING__SHIFT 0x0 30977298Sobrien#define SRBM_STATUS2__TST_RQ_PENDING_MASK 0x2 31077298Sobrien#define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1 31177298Sobrien#define SRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x4 31277298Sobrien#define SRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x2 31377298Sobrien#define SRBM_STATUS2__VCE0_RQ_PENDING_MASK 0x8 31478828Sobrien#define SRBM_STATUS2__VCE0_RQ_PENDING__SHIFT 0x3 31577298Sobrien#define SRBM_STATUS2__XSP_BUSY_MASK 0x10 31677298Sobrien#define SRBM_STATUS2__XSP_BUSY__SHIFT 0x4 31777298Sobrien#define SRBM_STATUS2__SDMA_BUSY_MASK 0x20 31877298Sobrien#define SRBM_STATUS2__SDMA_BUSY__SHIFT 0x5 31977298Sobrien#define SRBM_STATUS2__SDMA1_BUSY_MASK 0x40 32077298Sobrien#define SRBM_STATUS2__SDMA1_BUSY__SHIFT 0x6 32177298Sobrien#define SRBM_STATUS2__VCE0_BUSY_MASK 0x80 32278828Sobrien#define SRBM_STATUS2__VCE0_BUSY__SHIFT 0x7 32377298Sobrien#define SRBM_STATUS2__XDMA_BUSY_MASK 0x100 32477298Sobrien#define SRBM_STATUS2__XDMA_BUSY__SHIFT 0x8 32577298Sobrien#define SRBM_STATUS2__CHUB_BUSY_MASK 0x200 32677298Sobrien#define SRBM_STATUS2__CHUB_BUSY__SHIFT 0x9 32777298Sobrien#define SRBM_STATUS2__SDMA2_BUSY_MASK 0x400 32877298Sobrien#define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa 32977298Sobrien#define SRBM_STATUS2__SDMA3_BUSY_MASK 0x800 33077298Sobrien#define SRBM_STATUS2__SDMA3_BUSY__SHIFT 0xb 33177298Sobrien#define SRBM_STATUS2__SAMSCP_BUSY_MASK 0x1000 33277298Sobrien#define SRBM_STATUS2__SAMSCP_BUSY__SHIFT 0xc 33377298Sobrien#define SRBM_STATUS2__ISP_BUSY_MASK 0x2000 33477298Sobrien#define SRBM_STATUS2__ISP_BUSY__SHIFT 0xd 33577298Sobrien#define SRBM_STATUS2__VCE1_BUSY_MASK 0x4000 33677298Sobrien#define SRBM_STATUS2__VCE1_BUSY__SHIFT 0xe 33777298Sobrien#define SRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x10000 33877298Sobrien#define SRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x10 33977298Sobrien#define SRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x20000 34077298Sobrien#define SRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x11 34177298Sobrien#define SRBM_STATUS2__SAMSCP_RQ_PENDING_MASK 0x40000 34277298Sobrien#define SRBM_STATUS2__SAMSCP_RQ_PENDING__SHIFT 0x12 34377298Sobrien#define SRBM_STATUS2__ISP_RQ_PENDING_MASK 0x80000 34477298Sobrien#define SRBM_STATUS2__ISP_RQ_PENDING__SHIFT 0x13 34577298Sobrien#define SRBM_STATUS2__VCE1_RQ_PENDING_MASK 0x100000 34677298Sobrien#define SRBM_STATUS2__VCE1_RQ_PENDING__SHIFT 0x14 34777298Sobrien#define SRBM_STATUS__UVD_RQ_PENDING_MASK 0x2 34877298Sobrien#define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1 34977298Sobrien#define SRBM_STATUS__SAMMSP_RQ_PENDING_MASK 0x4 35077298Sobrien#define SRBM_STATUS__SAMMSP_RQ_PENDING__SHIFT 0x2 35177298Sobrien#define SRBM_STATUS__ACP_RQ_PENDING_MASK 0x8 35277298Sobrien#define SRBM_STATUS__ACP_RQ_PENDING__SHIFT 0x3 35377298Sobrien#define SRBM_STATUS__SMU_RQ_PENDING_MASK 0x10 35477298Sobrien#define SRBM_STATUS__SMU_RQ_PENDING__SHIFT 0x4 35577298Sobrien#define SRBM_STATUS__GRBM_RQ_PENDING_MASK 0x20 35678828Sobrien#define SRBM_STATUS__GRBM_RQ_PENDING__SHIFT 0x5 35777298Sobrien#define SRBM_STATUS__HI_RQ_PENDING_MASK 0x40 35877298Sobrien#define SRBM_STATUS__HI_RQ_PENDING__SHIFT 0x6 35977298Sobrien#define SRBM_STATUS__VMC_BUSY_MASK 0x100 36077298Sobrien#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8 36177298Sobrien#define SRBM_STATUS__MCB_BUSY_MASK 0x200 36277298Sobrien#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9 36377298Sobrien#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 36477298Sobrien#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa 36577298Sobrien#define SRBM_STATUS__MCC_BUSY_MASK 0x800 36677298Sobrien#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb 36777298Sobrien#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 36877298Sobrien#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc 36977298Sobrien#define SRBM_STATUS__VMC1_BUSY_MASK 0x2000 37077298Sobrien#define SRBM_STATUS__VMC1_BUSY__SHIFT 0xd 37177298Sobrien#define SRBM_STATUS__SEM_BUSY_MASK 0x4000 37277298Sobrien#define SRBM_STATUS__SEM_BUSY__SHIFT 0xe 37377298Sobrien#define SRBM_STATUS__ACP_BUSY_MASK 0x10000 37477298Sobrien#define SRBM_STATUS__ACP_BUSY__SHIFT 0x10 37577298Sobrien#define SRBM_STATUS__IH_BUSY_MASK 0x20000 37677298Sobrien#define SRBM_STATUS__IH_BUSY__SHIFT 0x11 37777298Sobrien#define SRBM_STATUS__UVD_BUSY_MASK 0x80000 37877298Sobrien#define SRBM_STATUS__UVD_BUSY__SHIFT 0x13 37977298Sobrien#define SRBM_STATUS__SAMMSP_BUSY_MASK 0x100000 38077298Sobrien#define SRBM_STATUS__SAMMSP_BUSY__SHIFT 0x14 38177298Sobrien#define SRBM_STATUS__GCATCL2_BUSY_MASK 0x200000 38277298Sobrien#define SRBM_STATUS__GCATCL2_BUSY__SHIFT 0x15 38377298Sobrien#define SRBM_STATUS__OSATCL2_BUSY_MASK 0x400000 38477298Sobrien#define SRBM_STATUS__OSATCL2_BUSY__SHIFT 0x16 38577298Sobrien#define SRBM_STATUS__BIF_BUSY_MASK 0x20000000 38677298Sobrien#define SRBM_STATUS__BIF_BUSY__SHIFT 0x1d 38777298Sobrien#define SRBM_STATUS3__MCC0_BUSY_MASK 0x1 38877298Sobrien#define SRBM_STATUS3__MCC0_BUSY__SHIFT 0x0 38977298Sobrien#define SRBM_STATUS3__MCC1_BUSY_MASK 0x2 39077298Sobrien#define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1 39177298Sobrien#define SRBM_STATUS3__MCC2_BUSY_MASK 0x4 39277298Sobrien#define SRBM_STATUS3__MCC2_BUSY__SHIFT 0x2 39377298Sobrien#define SRBM_STATUS3__MCC3_BUSY_MASK 0x8 39477298Sobrien#define SRBM_STATUS3__MCC3_BUSY__SHIFT 0x3 39577298Sobrien#define SRBM_STATUS3__MCC4_BUSY_MASK 0x10 39677298Sobrien#define SRBM_STATUS3__MCC4_BUSY__SHIFT 0x4 39777298Sobrien#define SRBM_STATUS3__MCC5_BUSY_MASK 0x20 39877298Sobrien#define SRBM_STATUS3__MCC5_BUSY__SHIFT 0x5 39977298Sobrien#define SRBM_STATUS3__MCC6_BUSY_MASK 0x40 40077298Sobrien#define SRBM_STATUS3__MCC6_BUSY__SHIFT 0x6 40177298Sobrien#define SRBM_STATUS3__MCC7_BUSY_MASK 0x80 40277298Sobrien#define SRBM_STATUS3__MCC7_BUSY__SHIFT 0x7 40377298Sobrien#define SRBM_STATUS3__MCD0_BUSY_MASK 0x100 40477298Sobrien#define SRBM_STATUS3__MCD0_BUSY__SHIFT 0x8 40577298Sobrien#define SRBM_STATUS3__MCD1_BUSY_MASK 0x200 40678828Sobrien#define SRBM_STATUS3__MCD1_BUSY__SHIFT 0x9 40777298Sobrien#define SRBM_STATUS3__MCD2_BUSY_MASK 0x400 40877298Sobrien#define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa 40977298Sobrien#define SRBM_STATUS3__MCD3_BUSY_MASK 0x800 41077298Sobrien#define SRBM_STATUS3__MCD3_BUSY__SHIFT 0xb 41177298Sobrien#define SRBM_STATUS3__MCD4_BUSY_MASK 0x1000 41277298Sobrien#define SRBM_STATUS3__MCD4_BUSY__SHIFT 0xc 41377298Sobrien#define SRBM_STATUS3__MCD5_BUSY_MASK 0x2000 41477298Sobrien#define SRBM_STATUS3__MCD5_BUSY__SHIFT 0xd 41577298Sobrien#define SRBM_STATUS3__MCD6_BUSY_MASK 0x4000 41677298Sobrien#define SRBM_STATUS3__MCD6_BUSY__SHIFT 0xe 41777298Sobrien#define SRBM_STATUS3__MCD7_BUSY_MASK 0x8000 41877298Sobrien#define SRBM_STATUS3__MCD7_BUSY__SHIFT 0xf 41977298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1 42077298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ATCL2__SHIFT 0x0 42177298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_BIF_MASK 0x2 42277298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1 42377298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x4 42477298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x2 42577298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x8 42677298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x3 42777298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL_MASK 0x10 42877298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ROPLL__SHIFT 0x4 42978828Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_DC_MASK 0x20 43077298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_DC__SHIFT 0x5 43177298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x40 43277298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x6 43377298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK 0x100 43478828Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_GRBM__SHIFT 0x8 43577298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_HDP_MASK 0x200 43677298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_HDP__SHIFT 0x9 43777298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK 0x400 43877298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa 43961843Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_MC_MASK 0x800 44061843Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_MC__SHIFT 0xb 44161843Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_CHUB_MASK 0x1000 44261843Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_CHUB__SHIFT 0xc 44361843Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM_MASK 0x2000 44461843Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ESRAM__SHIFT 0xd 44577298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ROM_MASK 0x4000 44677298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ROM__SHIFT 0xe 44777298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK 0x8000 44877298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SEM__SHIFT 0xf 44977298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SMU_MASK 0x10000 45077298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SMU__SHIFT 0x10 45177298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK 0x20000 45277298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_VMC__SHIFT 0x11 45378828Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK 0x40000 45477298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_UVD__SHIFT 0x12 45577298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_XSP_MASK 0x80000 45677298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_XSP__SHIFT 0x13 45777298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK 0x100000 45877298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SDMA__SHIFT 0x14 45977298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_TST_MASK 0x200000 46077298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_TST__SHIFT 0x15 46177298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_REGBB_MASK 0x400000 46277298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_REGBB__SHIFT 0x16 46377298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ORB_MASK 0x800000 46477298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ORB__SHIFT 0x17 46577298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_VCE0_MASK 0x1000000 46677298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_VCE0__SHIFT 0x18 46777298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_XDMA_MASK 0x2000000 46877298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_XDMA__SHIFT 0x19 46977298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ACP_MASK 0x4000000 47077298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ACP__SHIFT 0x1a 47177298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP_MASK 0x8000000 47277298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SAMMSP__SHIFT 0x1b 47377298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP_MASK 0x10000000 47477298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_SAMSCP__SHIFT 0x1c 47577298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_GRN_MASK 0x20000000 47677298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_GRN__SHIFT 0x1d 47777298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ISP_MASK 0x40000000 47877298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_ISP__SHIFT 0x1e 47977298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_VCE1_MASK 0x80000000 48077298Sobrien#define SRBM_SOFT_RESET__SOFT_RESET_VCE1__SHIFT 0x1f 48177298Sobrien#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX_MASK 0x3f 48277298Sobrien#define SRBM_DEBUG_CNTL__SRBM_DEBUG_INDEX__SHIFT 0x0 48377298Sobrien#define SRBM_DEBUG_DATA__DATA_MASK 0xffffffff 48477298Sobrien#define SRBM_DEBUG_DATA__DATA__SHIFT 0x0 48577298Sobrien#define SRBM_CHIP_REVISION__CHIP_REVISION_MASK 0xff 48677298Sobrien#define SRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 48777298Sobrien#define CC_SYS_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 48877298Sobrien#define CC_SYS_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 48977298Sobrien#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 49077298Sobrien#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 49177298Sobrien#define CC_SYS_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 49277298Sobrien#define CC_SYS_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 49377298Sobrien#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 49477298Sobrien#define CC_SYS_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 49577298Sobrien#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 49677298Sobrien#define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 49777298Sobrien#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 49877298Sobrien#define GC_USER_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 49977298Sobrien#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 50077298Sobrien#define SRBM_MC_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 50177298Sobrien#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 50277298Sobrien#define SRBM_MC_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 50377298Sobrien#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 50477298Sobrien#define SRBM_SYS_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 50577298Sobrien#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 50677298Sobrien#define SRBM_SYS_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 50777298Sobrien#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 50877298Sobrien#define SRBM_VCE_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 50977298Sobrien#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 51077298Sobrien#define SRBM_VCE_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 51177298Sobrien#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 51277298Sobrien#define SRBM_UVD_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 51360484Sobrien#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 51460484Sobrien#define SRBM_UVD_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 51560484Sobrien#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 51660484Sobrien#define SRBM_SDMA_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 51760484Sobrien#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 51860484Sobrien#define SRBM_SDMA_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 51960484Sobrien#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 52060484Sobrien#define SRBM_SAM_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 52177298Sobrien#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 52277298Sobrien#define SRBM_SAM_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 52377298Sobrien#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf 52477298Sobrien#define SRBM_ISP_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 52577298Sobrien#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 52677298Sobrien#define SRBM_ISP_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 52760484Sobrien#define SRBM_DEBUG__IGNORE_RDY_MASK 0x1 52860484Sobrien#define SRBM_DEBUG__IGNORE_RDY__SHIFT 0x0 52960484Sobrien#define SRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x2 53060484Sobrien#define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1 53160484Sobrien#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x4 53260484Sobrien#define SRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x2 53360484Sobrien#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE_MASK 0x10 53460484Sobrien#define SRBM_DEBUG__SYS_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x4 53560484Sobrien#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE_MASK 0x20 53660484Sobrien#define SRBM_DEBUG__VCE_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x5 53760484Sobrien#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE_MASK 0x40 53860484Sobrien#define SRBM_DEBUG__UVD_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x6 53960484Sobrien#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE_MASK 0x80 54060484Sobrien#define SRBM_DEBUG__SDMA_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x7 54160484Sobrien#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE_MASK 0x100 54260484Sobrien#define SRBM_DEBUG__MC_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x8 54360484Sobrien#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE_MASK 0x200 54460484Sobrien#define SRBM_DEBUG__SAM_CLOCK_DOMAIN_OVERRIDE__SHIFT 0x9 54560484Sobrien#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE_MASK 0x400 54660484Sobrien#define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa 54760484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1 54860484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCB_RDY__SHIFT 0x0 54960484Sobrien#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY_MASK 0x2 55060484Sobrien#define SRBM_DEBUG_SNAPSHOT__ROPLL_RDY__SHIFT 0x1 55160484Sobrien#define SRBM_DEBUG_SNAPSHOT__SMU_RDY_MASK 0x4 55260484Sobrien#define SRBM_DEBUG_SNAPSHOT__SMU_RDY__SHIFT 0x2 55360484Sobrien#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY_MASK 0x8 55460484Sobrien#define SRBM_DEBUG_SNAPSHOT__SAMMSP_RDY__SHIFT 0x3 55560484Sobrien#define SRBM_DEBUG_SNAPSHOT__ACP_RDY_MASK 0x10 55660484Sobrien#define SRBM_DEBUG_SNAPSHOT__ACP_RDY__SHIFT 0x4 55760484Sobrien#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY_MASK 0x20 55860484Sobrien#define SRBM_DEBUG_SNAPSHOT__GRBM_RDY__SHIFT 0x5 55960484Sobrien#define SRBM_DEBUG_SNAPSHOT__DC_RDY_MASK 0x40 56060484Sobrien#define SRBM_DEBUG_SNAPSHOT__DC_RDY__SHIFT 0x6 56160484Sobrien#define SRBM_DEBUG_SNAPSHOT__BIF_RDY_MASK 0x80 56260484Sobrien#define SRBM_DEBUG_SNAPSHOT__BIF_RDY__SHIFT 0x7 56360484Sobrien#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY_MASK 0x100 56460484Sobrien#define SRBM_DEBUG_SNAPSHOT__XDMA_RDY__SHIFT 0x8 56560484Sobrien#define SRBM_DEBUG_SNAPSHOT__UVD_RDY_MASK 0x200 56660484Sobrien#define SRBM_DEBUG_SNAPSHOT__UVD_RDY__SHIFT 0x9 56760484Sobrien#define SRBM_DEBUG_SNAPSHOT__XSP_RDY_MASK 0x400 56860484Sobrien#define SRBM_DEBUG_SNAPSHOT__XSP_RDY__SHIFT 0xa 56960484Sobrien#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY_MASK 0x800 57060484Sobrien#define SRBM_DEBUG_SNAPSHOT__REGBB_RDY__SHIFT 0xb 57160484Sobrien#define SRBM_DEBUG_SNAPSHOT__ORB_RDY_MASK 0x1000 57260484Sobrien#define SRBM_DEBUG_SNAPSHOT__ORB_RDY__SHIFT 0xc 57360484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY_MASK 0x2000 57460484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD7_RDY__SHIFT 0xd 57560484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY_MASK 0x4000 57660484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD6_RDY__SHIFT 0xe 57760484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY_MASK 0x8000 57860484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD5_RDY__SHIFT 0xf 57960484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY_MASK 0x10000 58060484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD4_RDY__SHIFT 0x10 58160484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY_MASK 0x20000 58260484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD3_RDY__SHIFT 0x11 58360484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY_MASK 0x40000 58460484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD2_RDY__SHIFT 0x12 58560484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY_MASK 0x80000 58660484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD1_RDY__SHIFT 0x13 58760484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY_MASK 0x100000 58860484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCD0_RDY__SHIFT 0x14 58960484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY_MASK 0x200000 59060484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC7_RDY__SHIFT 0x15 59160484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY_MASK 0x400000 59260484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC6_RDY__SHIFT 0x16 59360484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY_MASK 0x800000 59460484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC5_RDY__SHIFT 0x17 59560484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY_MASK 0x1000000 59678828Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC4_RDY__SHIFT 0x18 59760484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY_MASK 0x2000000 59860484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC3_RDY__SHIFT 0x19 59960484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY_MASK 0x4000000 60060484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC2_RDY__SHIFT 0x1a 60160484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY_MASK 0x8000000 60260484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC1_RDY__SHIFT 0x1b 60360484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY_MASK 0x10000000 60460484Sobrien#define SRBM_DEBUG_SNAPSHOT__MCC0_RDY__SHIFT 0x1c 60560484Sobrien#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY_MASK 0x20000000 60660484Sobrien#define SRBM_DEBUG_SNAPSHOT__VCE0_RDY__SHIFT 0x1d 60760484Sobrien#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY_MASK 0x40000000 60860484Sobrien#define SRBM_DEBUG_SNAPSHOT__SAMSCP_RDY__SHIFT 0x1e 60960484Sobrien#define SRBM_DEBUG_SNAPSHOT__ISP_RDY_MASK 0x80000000 61060484Sobrien#define SRBM_DEBUG_SNAPSHOT__ISP_RDY__SHIFT 0x1f 61160484Sobrien#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1 61260484Sobrien#define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY__SHIFT 0x0 61360484Sobrien#define SRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc 61460484Sobrien#define SRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 61560484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3_MASK 0x40000 61660484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA3__SHIFT 0x12 61760484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2_MASK 0x80000 61860484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA2__SHIFT 0x13 61960484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_VCE0_MASK 0x100000 62060484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_VCE0__SHIFT 0x14 62160484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1_MASK 0x200000 62260484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA1__SHIFT 0x15 62360484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_TST_MASK 0x400000 62460484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_TST__SHIFT 0x16 62560484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP_MASK 0x800000 62660484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SAMMSP__SHIFT 0x17 62760484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_HI_MASK 0x1000000 62860484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_HI__SHIFT 0x18 62960484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_GRBM_MASK 0x2000000 63060484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_GRBM__SHIFT 0x19 63160484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SMU_MASK 0x4000000 63260484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SMU__SHIFT 0x1a 63360484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP_MASK 0x8000000 63460484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SAMSCP__SHIFT 0x1b 63560484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA_MASK 0x10000000 63660484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_SDMA__SHIFT 0x1c 63760484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_UVD_MASK 0x20000000 63860484Sobrien#define SRBM_READ_ERROR__READ_REQUESTER_UVD__SHIFT 0x1d 63960484Sobrien#define SRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 64060484Sobrien#define SRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 64160484Sobrien#define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1 64260484Sobrien#define SRBM_READ_ERROR2__READ_REQUESTER_ACP__SHIFT 0x0 64360484Sobrien#define SRBM_READ_ERROR2__READ_REQUESTER_ISP_MASK 0x2 64460484Sobrien#define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1 64560484Sobrien#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1_MASK 0x4 64660484Sobrien#define SRBM_READ_ERROR2__READ_REQUESTER_VCE1__SHIFT 0x2 64760484Sobrien#define SRBM_READ_ERROR2__READ_VF_MASK 0x800000 64860484Sobrien#define SRBM_READ_ERROR2__READ_VF__SHIFT 0x17 64960484Sobrien#define SRBM_READ_ERROR2__READ_VFID_MASK 0xf000000 65060484Sobrien#define SRBM_READ_ERROR2__READ_VFID__SHIFT 0x18 65160484Sobrien#define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1 65260484Sobrien#define SRBM_INT_CNTL__RDERR_INT_MASK__SHIFT 0x0 65360484Sobrien#define SRBM_INT_CNTL__RAERR_INT_MASK_MASK 0x2 65460484Sobrien#define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1 65560484Sobrien#define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1 65660484Sobrien#define SRBM_INT_STATUS__RDERR_INT_STAT__SHIFT 0x0 65760484Sobrien#define SRBM_INT_STATUS__RAERR_INT_STAT_MASK 0x2 65860484Sobrien#define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1 65960484Sobrien#define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1 66060484Sobrien#define SRBM_INT_ACK__RDERR_INT_ACK__SHIFT 0x0 66160484Sobrien#define SRBM_INT_ACK__RAERR_INT_ACK_MASK 0x2 66260484Sobrien#define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1 66360484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1 66460484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF__SHIFT 0x0 66560484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP_MASK 0x2 66660484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1 66760484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP_MASK 0x4 66860484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMSCP__SHIFT 0x2 66960484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP_MASK 0x8 67060484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SAMMSP__SHIFT 0x3 67160484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST_MASK 0x20 67260484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_TST__SHIFT 0x5 67360484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3_MASK 0x40 67460484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA3__SHIFT 0x6 67560484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2_MASK 0x80 67660484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA2__SHIFT 0x7 67760484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1_MASK 0x100 67860484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA1__SHIFT 0x8 67960484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0_MASK 0x200 68060484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SDMA0__SHIFT 0x9 68160484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD_MASK 0x400 68260484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_UVD__SHIFT 0xa 68360484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0_MASK 0x800 68460484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE0__SHIFT 0xb 68560484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM_MASK 0x1000 68660484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_GRBM__SHIFT 0xc 68760484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU_MASK 0x2000 68860484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMU__SHIFT 0xd 68960484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER_MASK 0x4000 69060484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_PEER__SHIFT 0xe 69160484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU_MASK 0x8000 69260484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_CPU__SHIFT 0xf 69360484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP_MASK 0x10000 69460484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ISP__SHIFT 0x10 69560484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1_MASK 0x20000 69660484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_VCE1__SHIFT 0x11 69760484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP_MASK 0x40000 69860484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_RLCHYP__SHIFT 0x12 69960484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP_MASK 0x80000 70060484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_SMUHYP__SHIFT 0x13 70160484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP_MASK 0x100000 70260484Sobrien#define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIFHYP__SHIFT 0x14 70360484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION_MASK 0x1000000 70460484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_FIREWALL_VIOLATION__SHIFT 0x18 70560484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW_MASK 0x2000000 70660484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_HAR_REGIONSIZE_OVERFLOW__SHIFT 0x19 70760484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW_MASK 0x4000000 70860484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_BIF_ADDR_OVERFLOW__SHIFT 0x1a 70960484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW_MASK 0x8000000 71060484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_REGIONSIZE_OVERFLOW__SHIFT 0x1b 71160484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION_MASK 0x10000000 71260484Sobrien#define SRBM_FIREWALL_ERROR_SRC__RAERR_P2SRP_FIREWALL_VIOLATION__SHIFT 0x1c 71360484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS_MASK 0x3fffc 71460484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_ADDRESS__SHIFT 0x2 71560484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF_MASK 0x80000 71660484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VF__SHIFT 0x13 71760484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID_MASK 0xf00000 71860484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__ACCESS_VFID__SHIFT 0x14 71960484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION_MASK 0x80000000 72060484Sobrien#define SRBM_FIREWALL_ERROR_ADDR__FIREWALL_VIOLATION__SHIFT 0x1f 72160484Sobrien#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR_MASK 0xffff 72260484Sobrien#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_ADDR__SHIFT 0x0 72360484Sobrien#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP_MASK 0x10000 72478828Sobrien#define SRBM_DSM_TRIG_CNTL0__DSM_TRIG_OP__SHIFT 0x10 72560484Sobrien#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD_MASK 0xffffffff 72660484Sobrien#define SRBM_DSM_TRIG_CNTL1__DSM_TRIG_WD__SHIFT 0x0 72760484Sobrien#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK_MASK 0xffff 72860484Sobrien#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_ADDR_MASK__SHIFT 0x0 72960484Sobrien#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK_MASK 0x10000 73060484Sobrien#define SRBM_DSM_TRIG_MASK0__DSM_TRIG_OP_MASK__SHIFT 0x10 73160484Sobrien#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK_MASK 0xffffffff 73260484Sobrien#define SRBM_DSM_TRIG_MASK1__DSM_TRIG_WD_MASK__SHIFT 0x0 73360484Sobrien#define SRBM_PERFMON_CNTL__PERFMON_STATE_MASK 0xf 73460484Sobrien#define SRBM_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 73560484Sobrien#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 73660484Sobrien#define SRBM_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 73760484Sobrien#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 73860484Sobrien#define SRBM_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 73960484Sobrien#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f 74060484Sobrien#define SRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 74160484Sobrien#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f 74260484Sobrien#define SRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 74360484Sobrien#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO_MASK 0xffffffff 74460484Sobrien#define SRBM_PERFCOUNTER0_LO__PERF_COUNT0_LO__SHIFT 0x0 74560484Sobrien#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI_MASK 0xffffffff 74660484Sobrien#define SRBM_PERFCOUNTER0_HI__PERF_COUNT0_HI__SHIFT 0x0 74760484Sobrien#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO_MASK 0xffffffff 74860484Sobrien#define SRBM_PERFCOUNTER1_LO__PERF_COUNT1_LO__SHIFT 0x0 74960484Sobrien#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI_MASK 0xffffffff 75060484Sobrien#define SRBM_PERFCOUNTER1_HI__PERF_COUNT1_HI__SHIFT 0x0 75160484Sobrien#define SRBM_CAM_INDEX__CAM_INDEX_MASK 0x3 75260484Sobrien#define SRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 75360484Sobrien#define SRBM_CAM_DATA__CAM_ADDR_MASK 0xffff 75460484Sobrien#define SRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 75560484Sobrien#define SRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 75660484Sobrien#define SRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 75760484Sobrien#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 75860484Sobrien#define SRBM_MC_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 75960484Sobrien#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 76060484Sobrien#define SRBM_MC_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 76160484Sobrien#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 76260484Sobrien#define SRBM_MC_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 76360484Sobrien#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 76477298Sobrien#define SRBM_MC_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 76560484Sobrien#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 76660484Sobrien#define SRBM_MC_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 76760484Sobrien#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 76860484Sobrien#define SRBM_MC_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 76960484Sobrien#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 77060484Sobrien#define SRBM_MC_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 77160484Sobrien#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 77260484Sobrien#define SRBM_MC_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 77360484Sobrien#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 77460484Sobrien#define SRBM_MC_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 77560484Sobrien#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 77660484Sobrien#define SRBM_MC_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 77760484Sobrien#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 77860484Sobrien#define SRBM_MC_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 77960484Sobrien#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 78060484Sobrien#define SRBM_MC_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 78160484Sobrien#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 78260484Sobrien#define SRBM_MC_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 78360484Sobrien#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 78460484Sobrien#define SRBM_MC_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 78560484Sobrien#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 78660484Sobrien#define SRBM_SYS_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 78760484Sobrien#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 78860484Sobrien#define SRBM_SYS_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 78960484Sobrien#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 79060484Sobrien#define SRBM_SYS_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 79160484Sobrien#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 79260484Sobrien#define SRBM_SYS_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 79360484Sobrien#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 79477298Sobrien#define SRBM_SYS_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 79560484Sobrien#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 79660484Sobrien#define SRBM_SYS_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 79760484Sobrien#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 79860484Sobrien#define SRBM_SYS_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 79960484Sobrien#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 80060484Sobrien#define SRBM_SYS_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 80160484Sobrien#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO_MASK 0xffff 80260484Sobrien#define SRBM_SYS_DOMAIN_ADDR4__ADDR_LO__SHIFT 0x0 80360484Sobrien#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI_MASK 0xffff0000 80460484Sobrien#define SRBM_SYS_DOMAIN_ADDR4__ADDR_HI__SHIFT 0x10 80560484Sobrien#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO_MASK 0xffff 80660484Sobrien#define SRBM_SYS_DOMAIN_ADDR5__ADDR_LO__SHIFT 0x0 80760484Sobrien#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI_MASK 0xffff0000 80860484Sobrien#define SRBM_SYS_DOMAIN_ADDR5__ADDR_HI__SHIFT 0x10 80960484Sobrien#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO_MASK 0xffff 81060484Sobrien#define SRBM_SYS_DOMAIN_ADDR6__ADDR_LO__SHIFT 0x0 81160484Sobrien#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI_MASK 0xffff0000 81260484Sobrien#define SRBM_SYS_DOMAIN_ADDR6__ADDR_HI__SHIFT 0x10 81360484Sobrien#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 81460484Sobrien#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 81560484Sobrien#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 81660484Sobrien#define SRBM_SDMA_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 81760484Sobrien#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 81860484Sobrien#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 81960484Sobrien#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 82060484Sobrien#define SRBM_SDMA_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 82160484Sobrien#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 82260484Sobrien#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 82360484Sobrien#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 82460484Sobrien#define SRBM_SDMA_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 82560484Sobrien#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO_MASK 0xffff 82660484Sobrien#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_LO__SHIFT 0x0 82760484Sobrien#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI_MASK 0xffff0000 82860484Sobrien#define SRBM_SDMA_DOMAIN_ADDR3__ADDR_HI__SHIFT 0x10 82960484Sobrien#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 83060484Sobrien#define SRBM_UVD_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 83160484Sobrien#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 83260484Sobrien#define SRBM_UVD_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 83360484Sobrien#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 83460484Sobrien#define SRBM_UVD_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 83560484Sobrien#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 83660484Sobrien#define SRBM_UVD_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 83760484Sobrien#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 83860484Sobrien#define SRBM_UVD_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 83960484Sobrien#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 84060484Sobrien#define SRBM_UVD_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 84160484Sobrien#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 84260484Sobrien#define SRBM_VCE_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 84360484Sobrien#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 84460484Sobrien#define SRBM_VCE_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 84560484Sobrien#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 84660484Sobrien#define SRBM_VCE_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 84760484Sobrien#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 84860484Sobrien#define SRBM_VCE_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 84960484Sobrien#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 85060484Sobrien#define SRBM_VCE_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 85160484Sobrien#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 85260484Sobrien#define SRBM_VCE_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 85360484Sobrien#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 85460484Sobrien#define SRBM_SAM_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 85560484Sobrien#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 85660484Sobrien#define SRBM_SAM_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 85760484Sobrien#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 85860484Sobrien#define SRBM_SAM_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 85960484Sobrien#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 86060484Sobrien#define SRBM_SAM_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 86138889Sjdp#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 86238889Sjdp#define SRBM_SAM_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 86338889Sjdp#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 86438889Sjdp#define SRBM_SAM_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 86538889Sjdp#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO_MASK 0xffff 86638889Sjdp#define SRBM_ISP_DOMAIN_ADDR0__ADDR_LO__SHIFT 0x0 86738889Sjdp#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI_MASK 0xffff0000 86838889Sjdp#define SRBM_ISP_DOMAIN_ADDR0__ADDR_HI__SHIFT 0x10 86938889Sjdp#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO_MASK 0xffff 87038889Sjdp#define SRBM_ISP_DOMAIN_ADDR1__ADDR_LO__SHIFT 0x0 87138889Sjdp#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI_MASK 0xffff0000 87238889Sjdp#define SRBM_ISP_DOMAIN_ADDR1__ADDR_HI__SHIFT 0x10 87338889Sjdp#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO_MASK 0xffff 87438889Sjdp#define SRBM_ISP_DOMAIN_ADDR2__ADDR_LO__SHIFT 0x0 87538889Sjdp#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI_MASK 0xffff0000 87638889Sjdp#define SRBM_ISP_DOMAIN_ADDR2__ADDR_HI__SHIFT 0x10 87738889Sjdp#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL_MASK 0xf 87838889Sjdp#define SYS_GRBM_GFX_INDEX_SELECT__SYS_GRBM_GFX_INDEX_SEL__SHIFT 0x0 87938889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX_MASK 0xff 88038889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_INDEX__SHIFT 0x0 88138889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX_MASK 0xff00 88238889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SH_INDEX__SHIFT 0x8 88338889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX_MASK 0xff0000 88438889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT 0x10 88538889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK 0x20000000 88638889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d 88760484Sobrien#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 88838889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 88938889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES_MASK 0x80000000 89038889Sjdp#define SYS_GRBM_GFX_INDEX_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f 89138889Sjdp#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL_MASK 0xf 89238889Sjdp#define SRBM_GFX_CNTL_SELECT__SRBM_GFX_CNTL_SEL__SHIFT 0x0 89338889Sjdp#define SRBM_GFX_CNTL_DATA__PIPEID_MASK 0x3 89438889Sjdp#define SRBM_GFX_CNTL_DATA__PIPEID__SHIFT 0x0 89538889Sjdp#define SRBM_GFX_CNTL_DATA__MEID_MASK 0xc 89638889Sjdp#define SRBM_GFX_CNTL_DATA__MEID__SHIFT 0x2 89738889Sjdp#define SRBM_GFX_CNTL_DATA__VMID_MASK 0xf0 89838889Sjdp#define SRBM_GFX_CNTL_DATA__VMID__SHIFT 0x4 89938889Sjdp#define SRBM_GFX_CNTL_DATA__QUEUEID_MASK 0x700 90038889Sjdp#define SRBM_GFX_CNTL_DATA__QUEUEID__SHIFT 0x8 90138889Sjdp#define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1 90238889Sjdp#define SRBM_VF_ENABLE__VF_ENABLE__SHIFT 0x0 90338889Sjdp#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1 90438889Sjdp#define SRBM_VIRT_CNTL__VF_WRITE_ENABLE__SHIFT 0x0 90538889Sjdp#define SRBM_VIRT_RESET_REQ__VF_MASK 0xffff 90638889Sjdp#define SRBM_VIRT_RESET_REQ__VF__SHIFT 0x0 90738889Sjdp#define SRBM_VIRT_RESET_REQ__PF_MASK 0x80000000 90838889Sjdp#define SRBM_VIRT_RESET_REQ__PF__SHIFT 0x1f 90938889Sjdp#define SDMA0_UCODE_ADDR__VALUE_MASK 0xfff 91038889Sjdp#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 91138889Sjdp#define SDMA0_UCODE_DATA__VALUE_MASK 0xffffffff 91238889Sjdp#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 91338889Sjdp#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 91438889Sjdp#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 91538889Sjdp#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0xf 91638889Sjdp#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 91738889Sjdp#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 91838889Sjdp#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 91938889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 92038889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 92138889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 92238889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 92338889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 92438889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 92538889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 92638889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 92738889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 92838889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 92938889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 93038889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 93138889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 93238889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 93338889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 93438889Sjdp#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 93538889Sjdp#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1 93638889Sjdp#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 93738889Sjdp#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 93838889Sjdp#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 93938889Sjdp#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x8 94038889Sjdp#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 94138889Sjdp#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 94238889Sjdp#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 94338889Sjdp#define SDMA0_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 94438889Sjdp#define SDMA0_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 94538889Sjdp#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 94638889Sjdp#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 94738889Sjdp#define SDMA0_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 94838889Sjdp#define SDMA0_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 94938889Sjdp#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 95038889Sjdp#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 95138889Sjdp#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 95238889Sjdp#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 95338889Sjdp#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 95438889Sjdp#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 95538889Sjdp#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 95660484Sobrien#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 95738889Sjdp#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 95838889Sjdp#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 95938889Sjdp#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 96038889Sjdp#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 96138889Sjdp#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 96238889Sjdp#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 96338889Sjdp#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 96438889Sjdp#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 96538889Sjdp#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 96638889Sjdp#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 96738889Sjdp#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 96838889Sjdp#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 96938889Sjdp#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 97038889Sjdp#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 97138889Sjdp#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 97238889Sjdp#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 97338889Sjdp#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 97438889Sjdp#define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 97538889Sjdp#define SDMA0_HASH__CHANNEL_BITS_MASK 0x7 97638889Sjdp#define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 97738889Sjdp#define SDMA0_HASH__BANK_BITS_MASK 0x70 97838889Sjdp#define SDMA0_HASH__BANK_BITS__SHIFT 0x4 97938889Sjdp#define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x700 98038889Sjdp#define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 98138889Sjdp#define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x7000 98238889Sjdp#define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc 98338889Sjdp#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 98438889Sjdp#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 98538889Sjdp#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 98638889Sjdp#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 98738889Sjdp#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 98838889Sjdp#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 98938889Sjdp#define SDMA0_PROGRAM__STREAM_MASK 0xffffffff 99038889Sjdp#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 99138889Sjdp#define SDMA0_STATUS_REG__IDLE_MASK 0x1 99238889Sjdp#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 99338889Sjdp#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x2 99438889Sjdp#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 99538889Sjdp#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x4 99638889Sjdp#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 99738889Sjdp#define SDMA0_STATUS_REG__RB_FULL_MASK 0x8 99838889Sjdp#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 99938889Sjdp#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x10 100038889Sjdp#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 100138889Sjdp#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x20 100238889Sjdp#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 100338889Sjdp#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x40 100438889Sjdp#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 100538889Sjdp#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x80 100638889Sjdp#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 100738889Sjdp#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x100 100838889Sjdp#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 100938889Sjdp#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x200 101038889Sjdp#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 101138889Sjdp#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x400 101238889Sjdp#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 101338889Sjdp#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 101438889Sjdp#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 101538889Sjdp#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x1000 101638889Sjdp#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 101738889Sjdp#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x2000 101838889Sjdp#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 101938889Sjdp#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x4000 102038889Sjdp#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 102138889Sjdp#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 102238889Sjdp#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 102338889Sjdp#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 102438889Sjdp#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 102538889Sjdp#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 102638889Sjdp#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 102738889Sjdp#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 102838889Sjdp#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 102938889Sjdp#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x80000 103038889Sjdp#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 103138889Sjdp#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 103238889Sjdp#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 103338889Sjdp#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 103438889Sjdp#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 103538889Sjdp#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 103638889Sjdp#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 103738889Sjdp#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 103838889Sjdp#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 103938889Sjdp#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x4000000 104038889Sjdp#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 104160484Sobrien#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 104238889Sjdp#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 104338889Sjdp#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 104438889Sjdp#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 104538889Sjdp#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000 104660484Sobrien#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 104738889Sjdp#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 104838889Sjdp#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 104938889Sjdp#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 105038889Sjdp#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 105138889Sjdp#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x2 105238889Sjdp#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 105338889Sjdp#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 105438889Sjdp#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 105538889Sjdp#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 105638889Sjdp#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 105738889Sjdp#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 105833965Sjdp#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 105933965Sjdp#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x20 106033965Sjdp#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 106133965Sjdp#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x40 106233965Sjdp#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 106333965Sjdp#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 106433965Sjdp#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 106533965Sjdp#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 106633965Sjdp#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 106733965Sjdp#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 106833965Sjdp#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 106933965Sjdp#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 107033965Sjdp#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 107133965Sjdp#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x20000 107233965Sjdp#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 107333965Sjdp#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x40000 107433965Sjdp#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 107533965Sjdp#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 107633965Sjdp#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 107733965Sjdp#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 107833965Sjdp#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 107933965Sjdp#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 108033965Sjdp#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 108133965Sjdp#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 108233965Sjdp#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 108333965Sjdp#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 108433965Sjdp#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 108533965Sjdp#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 108633965Sjdp#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 108733965Sjdp#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 108833965Sjdp#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 108933965Sjdp#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 109033965Sjdp#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 109133965Sjdp#define SDMA0_F32_CNTL__HALT_MASK 0x1 109233965Sjdp#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 109333965Sjdp#define SDMA0_F32_CNTL__STEP_MASK 0x2 109433965Sjdp#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 109533965Sjdp#define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 109633965Sjdp#define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 109733965Sjdp#define SDMA0_FREEZE__FREEZE_MASK 0x10 109833965Sjdp#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 109933965Sjdp#define SDMA0_FREEZE__FROZEN_MASK 0x20 110033965Sjdp#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 110133965Sjdp#define SDMA0_FREEZE__F32_FREEZE_MASK 0x40 110233965Sjdp#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 110333965Sjdp#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf 110433965Sjdp#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 110533965Sjdp#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 110633965Sjdp#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 110733965Sjdp#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000 110833965Sjdp#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 110933965Sjdp#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0xf 111033965Sjdp#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 111133965Sjdp#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0xffff00 111233965Sjdp#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 111333965Sjdp#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000 111433965Sjdp#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 111533965Sjdp#define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1 111633965Sjdp#define SDMA_POWER_GATING__PG_CNTL_ENABLE__SHIFT 0x0 111733965Sjdp#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE_MASK 0x2 111833965Sjdp#define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1 111933965Sjdp#define SDMA_POWER_GATING__PG_STATE_VALID_MASK 0x4 112033965Sjdp#define SDMA_POWER_GATING__PG_STATE_VALID__SHIFT 0x2 112160484Sobrien#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x30 112260484Sobrien#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 112360484Sobrien#define SDMA_POWER_GATING__SDMA0_ON_CONDITION_MASK 0x40 112460484Sobrien#define SDMA_POWER_GATING__SDMA0_ON_CONDITION__SHIFT 0x6 112533965Sjdp#define SDMA_POWER_GATING__SDMA1_ON_CONDITION_MASK 0x80 112633965Sjdp#define SDMA_POWER_GATING__SDMA1_ON_CONDITION__SHIFT 0x7 112733965Sjdp#define SDMA_POWER_GATING__POWER_OFF_DELAY_MASK 0xfff00 112833965Sjdp#define SDMA_POWER_GATING__POWER_OFF_DELAY__SHIFT 0x8 112933965Sjdp#define SDMA_POWER_GATING__POWER_ON_DELAY_MASK 0xfff00000 113033965Sjdp#define SDMA_POWER_GATING__POWER_ON_DELAY__SHIFT 0x14 113133965Sjdp#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0xff 113233965Sjdp#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 113333965Sjdp#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x100 113433965Sjdp#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 113533965Sjdp#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x200 113633965Sjdp#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 113733965Sjdp#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x400 113833965Sjdp#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 113960484Sobrien#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x800 114033965Sjdp#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 114133965Sjdp#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x1000 114233965Sjdp#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 114333965Sjdp#define SDMA_PGFSM_CONFIG__READ_MASK 0x2000 114433965Sjdp#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 114533965Sjdp#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000 114633965Sjdp#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 114733965Sjdp#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000 114833965Sjdp#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 114933965Sjdp#define SDMA_PGFSM_WRITE__VALUE_MASK 0xffffffff 115033965Sjdp#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 115133965Sjdp#define SDMA_PGFSM_READ__VALUE_MASK 0xffffff 115233965Sjdp#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 115333965Sjdp#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x2 115433965Sjdp#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 115533965Sjdp#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 115633965Sjdp#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 115733965Sjdp#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x3ff 115833965Sjdp#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 115933965Sjdp#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 116033965Sjdp#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 116133965Sjdp#define SDMA0_ID__DEVICE_ID_MASK 0xff 116233965Sjdp#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 116333965Sjdp#define SDMA0_VERSION__VALUE_MASK 0xffff 116433965Sjdp#define SDMA0_VERSION__VALUE__SHIFT 0x0 116533965Sjdp#define SDMA0_STATUS2_REG__ID_MASK 0x3 116633965Sjdp#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 116733965Sjdp#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc 116833965Sjdp#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 116933965Sjdp#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xffff0000 117033965Sjdp#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 117133965Sjdp#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 117233965Sjdp#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 117333965Sjdp#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 117433965Sjdp#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 117533965Sjdp#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 117633965Sjdp#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 117733965Sjdp#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 117833965Sjdp#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 117933965Sjdp#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 118033965Sjdp#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 118133965Sjdp#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 118233965Sjdp#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 118333965Sjdp#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 118433965Sjdp#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 118538889Sjdp#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 118638889Sjdp#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 118738889Sjdp#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xffffffff 118838889Sjdp#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 118933965Sjdp#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 119033965Sjdp#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 119133965Sjdp#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 119233965Sjdp#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x2 119333965Sjdp#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 119433965Sjdp#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x2 119533965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 119633965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 119733965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 119833965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 119933965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 120033965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 120133965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 120233965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 120333965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 120433965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 120533965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 120633965Sjdp#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 120733965Sjdp#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 120833965Sjdp#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 120933965Sjdp#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 121033965Sjdp#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 121133965Sjdp#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 121233965Sjdp#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 121333965Sjdp#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 121433965Sjdp#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 121533965Sjdp#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 121633965Sjdp#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 121733965Sjdp#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 121833965Sjdp#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 121933965Sjdp#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 122033965Sjdp#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 122133965Sjdp#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 122233965Sjdp#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 122333965Sjdp#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 122433965Sjdp#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 122533965Sjdp#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 122633965Sjdp#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 122733965Sjdp#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0xfffff 122833965Sjdp#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 122933965Sjdp#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 123033965Sjdp#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 123133965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 123233965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 123333965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 123433965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 123533965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 123633965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 123733965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 123833965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 123933965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 124033965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 124133965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 124233965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 124333965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 124433965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 124533965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 124633965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 124733965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 124833965Sjdp#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 124933965Sjdp#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 125033965Sjdp#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 125133965Sjdp#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 125233965Sjdp#define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 125333965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 125433965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 125533965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 125633965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 125733965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 125833965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 125933965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 126033965Sjdp#define SDMA0_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 126133965Sjdp#define SDMA0_GFX_APE1_CNTL__BASE_MASK 0xffff 126233965Sjdp#define SDMA0_GFX_APE1_CNTL__BASE__SHIFT 0x0 126333965Sjdp#define SDMA0_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 126433965Sjdp#define SDMA0_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 126533965Sjdp#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 126633965Sjdp#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 126733965Sjdp#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 126833965Sjdp#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 126933965Sjdp#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 127033965Sjdp#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 127133965Sjdp#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 127233965Sjdp#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 127333965Sjdp#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 127433965Sjdp#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 127533965Sjdp#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 127633965Sjdp#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 127733965Sjdp#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 127833965Sjdp#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 127933965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 128033965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 128133965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 128233965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 128333965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 128433965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 128533965Sjdp#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 128633965Sjdp#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 128733965Sjdp#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 128833965Sjdp#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 128933965Sjdp#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 129033965Sjdp#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 129133965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 129233965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 129333965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 129433965Sjdp#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 129533965Sjdp#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xffffffff 129633965Sjdp#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 129733965Sjdp#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 129833965Sjdp#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 129933965Sjdp#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 130033965Sjdp#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 130133965Sjdp#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 130233965Sjdp#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 130333965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 130433965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 130533965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 130633965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 130733965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 130860484Sobrien#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 130933965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 131033965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 131133965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 131233965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 131333965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 131433965Sjdp#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 131533965Sjdp#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 131633965Sjdp#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 131733965Sjdp#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 131833965Sjdp#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 131933965Sjdp#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 132033965Sjdp#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 132133965Sjdp#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 132233965Sjdp#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 132333965Sjdp#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 132433965Sjdp#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 132533965Sjdp#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 132633965Sjdp#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 132733965Sjdp#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 132833965Sjdp#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 132933965Sjdp#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 133033965Sjdp#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 133133965Sjdp#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 133233965Sjdp#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 133333965Sjdp#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 133433965Sjdp#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 133533965Sjdp#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0xfffff 133633965Sjdp#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 133733965Sjdp#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 133833965Sjdp#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 133933965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 134033965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 134133965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 134233965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 134333965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 134433965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 134533965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 134633965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 134733965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 134833965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 134933965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 135033965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 135133965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 135233965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 135333965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 135433965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 135533965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 135633965Sjdp#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 135733965Sjdp#define SDMA0_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 135833965Sjdp#define SDMA0_RLC0_DOORBELL__OFFSET__SHIFT 0x0 135933965Sjdp#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000 136033965Sjdp#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 136133965Sjdp#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 136233965Sjdp#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 136333965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 136433965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 136533965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 136633965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 136733965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 136833965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 136933965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 137033965Sjdp#define SDMA0_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 137133965Sjdp#define SDMA0_RLC0_APE1_CNTL__BASE_MASK 0xffff 137233965Sjdp#define SDMA0_RLC0_APE1_CNTL__BASE__SHIFT 0x0 137333965Sjdp#define SDMA0_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 137433965Sjdp#define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 137533965Sjdp#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 137633965Sjdp#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 137733965Sjdp#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 137833965Sjdp#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 137933965Sjdp#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 138033965Sjdp#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 138133965Sjdp#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 138233965Sjdp#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 138333965Sjdp#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 138433965Sjdp#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 138533965Sjdp#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 138633965Sjdp#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 138733965Sjdp#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 138833965Sjdp#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 138933965Sjdp#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 139033965Sjdp#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 139133965Sjdp#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 139233965Sjdp#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 139333965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 139433965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 139533965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 139633965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 139733965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 139833965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 139933965Sjdp#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 140033965Sjdp#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 140133965Sjdp#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 140233965Sjdp#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 140333965Sjdp#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 140433965Sjdp#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 140533965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 140633965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 140733965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 140833965Sjdp#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 140933965Sjdp#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xffffffff 141033965Sjdp#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 141133965Sjdp#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 141233965Sjdp#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 141333965Sjdp#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 141433965Sjdp#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 141533965Sjdp#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 141633965Sjdp#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 141733965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 141833965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 141933965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 142033965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 142133965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 142233965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 142333965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 142433965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 142533965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 142633965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 142733965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 142833965Sjdp#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 142933965Sjdp#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 143033965Sjdp#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 143160484Sobrien#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 143233965Sjdp#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 143333965Sjdp#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 143433965Sjdp#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 143533965Sjdp#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 143633965Sjdp#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 143733965Sjdp#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 143833965Sjdp#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 143933965Sjdp#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 144033965Sjdp#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 144133965Sjdp#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 144233965Sjdp#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 144333965Sjdp#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 144433965Sjdp#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 144533965Sjdp#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 144633965Sjdp#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 144733965Sjdp#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 144833965Sjdp#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 144933965Sjdp#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0xfffff 145033965Sjdp#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 145133965Sjdp#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 145233965Sjdp#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 145333965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 145433965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 145533965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 145633965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 145733965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 145833965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 145933965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 146033965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 146133965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 146233965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 146333965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 146433965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 146533965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 146633965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 146733965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 146833965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 146933965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 147033965Sjdp#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 147133965Sjdp#define SDMA0_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 147233965Sjdp#define SDMA0_RLC1_DOORBELL__OFFSET__SHIFT 0x0 147333965Sjdp#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000 147433965Sjdp#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 147533965Sjdp#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 147633965Sjdp#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 147733965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 147833965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 147933965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 148033965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 148133965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 148233965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 148333965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 148433965Sjdp#define SDMA0_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 148533965Sjdp#define SDMA0_RLC1_APE1_CNTL__BASE_MASK 0xffff 148633965Sjdp#define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0 148733965Sjdp#define SDMA0_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 148833965Sjdp#define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 148933965Sjdp#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 149033965Sjdp#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 149133965Sjdp#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 149233965Sjdp#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 149333965Sjdp#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 149460484Sobrien#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 149560484Sobrien#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 149633965Sjdp#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 149733965Sjdp#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 149833965Sjdp#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 149933965Sjdp#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 150033965Sjdp#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 150133965Sjdp#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 150233965Sjdp#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 150333965Sjdp#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 150433965Sjdp#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 150533965Sjdp#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 150633965Sjdp#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 150733965Sjdp#define SDMA1_UCODE_ADDR__VALUE_MASK 0xfff 150833965Sjdp#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 150933965Sjdp#define SDMA1_UCODE_DATA__VALUE_MASK 0xffffffff 151033965Sjdp#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 151133965Sjdp#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x100 151233965Sjdp#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 151333965Sjdp#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0xf 151433965Sjdp#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 151533965Sjdp#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 151633965Sjdp#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 151733965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 151833965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 151933965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 152033965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 152133965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 152233965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 152333965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 152433965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 152533965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 152633965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 152733965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 152833965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 152933965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 153033965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 153133965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 153233965Sjdp#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 153333965Sjdp#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1 153433965Sjdp#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 153533965Sjdp#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x4 153633965Sjdp#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 153733965Sjdp#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x8 153833965Sjdp#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 153933965Sjdp#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x10 154033965Sjdp#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 154133965Sjdp#define SDMA1_CNTL__MC_WRREQ_CREDIT_MASK 0x1f800 154233965Sjdp#define SDMA1_CNTL__MC_WRREQ_CREDIT__SHIFT 0xb 154333965Sjdp#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x40000 154433965Sjdp#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 154533965Sjdp#define SDMA1_CNTL__MC_RDREQ_CREDIT_MASK 0xfc00000 154633965Sjdp#define SDMA1_CNTL__MC_RDREQ_CREDIT__SHIFT 0x16 154733965Sjdp#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000 154833965Sjdp#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 154933965Sjdp#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000 155033965Sjdp#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 155133965Sjdp#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000 155233965Sjdp#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 155360484Sobrien#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1 155433965Sjdp#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 155533965Sjdp#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x2 155633965Sjdp#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 155733965Sjdp#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x4 155833965Sjdp#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 155933965Sjdp#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x10000 156033965Sjdp#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 156133965Sjdp#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x100000 156233965Sjdp#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 156333965Sjdp#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x800000 156433965Sjdp#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 156533965Sjdp#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0xc000000 156633965Sjdp#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 156733965Sjdp#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000 156833965Sjdp#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 156933965Sjdp#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xc0000000 157033965Sjdp#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 157133965Sjdp#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 157233965Sjdp#define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 157333965Sjdp#define SDMA1_HASH__CHANNEL_BITS_MASK 0x7 157433965Sjdp#define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 157533965Sjdp#define SDMA1_HASH__BANK_BITS_MASK 0x70 157633965Sjdp#define SDMA1_HASH__BANK_BITS__SHIFT 0x4 157733965Sjdp#define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x700 157833965Sjdp#define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 157933965Sjdp#define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x7000 158033965Sjdp#define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc 158133965Sjdp#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xffffffff 158233965Sjdp#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 158333965Sjdp#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xfffffffc 158433965Sjdp#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 158533965Sjdp#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x3ffffc 158633965Sjdp#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 158733965Sjdp#define SDMA1_PROGRAM__STREAM_MASK 0xffffffff 158833965Sjdp#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 158933965Sjdp#define SDMA1_STATUS_REG__IDLE_MASK 0x1 159033965Sjdp#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 159133965Sjdp#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x2 159233965Sjdp#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 159333965Sjdp#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x4 159433965Sjdp#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 159533965Sjdp#define SDMA1_STATUS_REG__RB_FULL_MASK 0x8 159633965Sjdp#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 159733965Sjdp#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x10 159833965Sjdp#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 159933965Sjdp#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x20 160033965Sjdp#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 160133965Sjdp#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x40 160233965Sjdp#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 160333965Sjdp#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x80 160433965Sjdp#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 160533965Sjdp#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x100 160633965Sjdp#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 160760484Sobrien#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x200 160833965Sjdp#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 160933965Sjdp#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x400 161033965Sjdp#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 161133965Sjdp#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x800 161233965Sjdp#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 161333965Sjdp#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x1000 161433965Sjdp#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 161533965Sjdp#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x2000 161633965Sjdp#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 161733965Sjdp#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x4000 161833965Sjdp#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 161933965Sjdp#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x8000 162033965Sjdp#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 162133965Sjdp#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x10000 162233965Sjdp#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 162333965Sjdp#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x20000 162433965Sjdp#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 162533965Sjdp#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x40000 162633965Sjdp#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 162733965Sjdp#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x80000 162833965Sjdp#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 162933965Sjdp#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x100000 163033965Sjdp#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 163133965Sjdp#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x200000 163233965Sjdp#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 163333965Sjdp#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x400000 163433965Sjdp#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 163533965Sjdp#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x2000000 163633965Sjdp#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 163733965Sjdp#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x4000000 163833965Sjdp#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 163933965Sjdp#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x8000000 164033965Sjdp#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 164133965Sjdp#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000 164233965Sjdp#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 164333965Sjdp#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000 164433965Sjdp#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 164533965Sjdp#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000 164633965Sjdp#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 164733965Sjdp#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1 164833965Sjdp#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 164933965Sjdp#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x2 165033965Sjdp#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 165133965Sjdp#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x4 165233965Sjdp#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 165333965Sjdp#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x8 165433965Sjdp#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 165533965Sjdp#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x10 165633965Sjdp#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 165733965Sjdp#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x20 165833965Sjdp#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 165933965Sjdp#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x40 166033965Sjdp#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 166133965Sjdp#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x200 166233965Sjdp#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 166333965Sjdp#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x400 166433965Sjdp#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 166533965Sjdp#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x2000 166633965Sjdp#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 166733965Sjdp#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x4000 166833965Sjdp#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 166933965Sjdp#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x20000 167033965Sjdp#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 167133965Sjdp#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x40000 167233965Sjdp#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 167333965Sjdp#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1 167433965Sjdp#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 167533965Sjdp#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x2 167633965Sjdp#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 167733965Sjdp#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0xfc 167833965Sjdp#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 167933965Sjdp#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x100 168033965Sjdp#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0x8 168133965Sjdp#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x200 168233965Sjdp#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0x9 168333965Sjdp#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0xfc00 168433965Sjdp#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa 168533965Sjdp#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xffffffff 168633965Sjdp#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 168733965Sjdp#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xffffffff 168833965Sjdp#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 168933965Sjdp#define SDMA1_F32_CNTL__HALT_MASK 0x1 169033965Sjdp#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 169133965Sjdp#define SDMA1_F32_CNTL__STEP_MASK 0x2 169233965Sjdp#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 169333965Sjdp#define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0xfc 169433965Sjdp#define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 169533965Sjdp#define SDMA1_FREEZE__FREEZE_MASK 0x10 169633965Sjdp#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 169733965Sjdp#define SDMA1_FREEZE__FROZEN_MASK 0x20 169833965Sjdp#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 169933965Sjdp#define SDMA1_FREEZE__F32_FREEZE_MASK 0x40 170033965Sjdp#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 170133965Sjdp#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0xf 170233965Sjdp#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 170333965Sjdp#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0xffff00 170433965Sjdp#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 170533965Sjdp#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000 170633965Sjdp#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 170733965Sjdp#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0xf 170833965Sjdp#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 170933965Sjdp#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0xffff00 171033965Sjdp#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 171133965Sjdp#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000 171233965Sjdp#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 171333965Sjdp#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x2 171433965Sjdp#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 171533965Sjdp#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x4 171633965Sjdp#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 171733965Sjdp#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x3ff 171833965Sjdp#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 171933965Sjdp#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x3ff0000 172033965Sjdp#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 172133965Sjdp#define SDMA1_ID__DEVICE_ID_MASK 0xff 172233965Sjdp#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 172333965Sjdp#define SDMA1_VERSION__VALUE_MASK 0xffff 172433965Sjdp#define SDMA1_VERSION__VALUE__SHIFT 0x0 172533965Sjdp#define SDMA1_STATUS2_REG__ID_MASK 0x3 172633965Sjdp#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 172733965Sjdp#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0xfffc 172833965Sjdp#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 172933965Sjdp#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xffff0000 173033965Sjdp#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 173133965Sjdp#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1 173233965Sjdp#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 173333965Sjdp#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x3e 173433965Sjdp#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 173533965Sjdp#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 173633965Sjdp#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 173733965Sjdp#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 173833965Sjdp#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 173933965Sjdp#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 174033965Sjdp#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 174133965Sjdp#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 174233965Sjdp#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 174333965Sjdp#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x800000 174433965Sjdp#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 174533965Sjdp#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0xf000000 174633965Sjdp#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 174733965Sjdp#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xffffffff 174833965Sjdp#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 174933965Sjdp#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0xffffff 175033965Sjdp#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 175133965Sjdp#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xfffffffc 175233965Sjdp#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x2 175333965Sjdp#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xfffffffc 175433965Sjdp#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x2 175533965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 175633965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 175733965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 175833965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 175933965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 176033965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 176133965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 176233965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 176333965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 176433965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 176533965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 176633965Sjdp#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 176733965Sjdp#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 176833965Sjdp#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 176933965Sjdp#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 177033965Sjdp#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 177133965Sjdp#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1 177233965Sjdp#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 177333965Sjdp#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 177433965Sjdp#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 177533965Sjdp#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 177633965Sjdp#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 177733965Sjdp#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0xf0000 177833965Sjdp#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 177933965Sjdp#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x3ffffc 178033965Sjdp#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 178133965Sjdp#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x3ffffc 178233965Sjdp#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 178333965Sjdp#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xffffffe0 178433965Sjdp#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 178533965Sjdp#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xffffffff 178633965Sjdp#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 178733965Sjdp#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0xfffff 178833965Sjdp#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 178933965Sjdp#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 179033965Sjdp#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 179133965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1 179233965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 179333965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 179433965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 179533965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x4 179633965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 179733965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x8 179833965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 179933965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x70 180033965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 180133965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 180233965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 180333965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 180433965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 180533965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x200 180633965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 180733965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 180833965Sjdp#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 180933965Sjdp#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x10000 181033965Sjdp#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 181133965Sjdp#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0xf000000 181233965Sjdp#define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 181333965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1 181433965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__ATC__SHIFT 0x0 181533965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__PTR32_MASK 0x10 181633965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__PTR32__SHIFT 0x4 181733965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 181833965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 181933965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 182033965Sjdp#define SDMA1_GFX_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 182133965Sjdp#define SDMA1_GFX_APE1_CNTL__BASE_MASK 0xffff 182233965Sjdp#define SDMA1_GFX_APE1_CNTL__BASE__SHIFT 0x0 182333965Sjdp#define SDMA1_GFX_APE1_CNTL__LIMIT_MASK 0xffff0000 182433965Sjdp#define SDMA1_GFX_APE1_CNTL__LIMIT__SHIFT 0x10 182533965Sjdp#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0xfff 182633965Sjdp#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 182733965Sjdp#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 182833965Sjdp#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 182933965Sjdp#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 183033965Sjdp#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 183133965Sjdp#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xffffffff 183233965Sjdp#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 183333965Sjdp#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xffffffff 183433965Sjdp#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 183533965Sjdp#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x3fff 183633965Sjdp#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 183733965Sjdp#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1 183833965Sjdp#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 183933965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1 184033965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 184133965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x3e 184233965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 184333965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 184433965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 184533965Sjdp#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 184633965Sjdp#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 184733965Sjdp#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 184833965Sjdp#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 184933965Sjdp#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 185033965Sjdp#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 185133965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x800000 185233965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 185333965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0xf000000 185433965Sjdp#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 185533965Sjdp#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xffffffff 185633965Sjdp#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 185733965Sjdp#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0xffffff 185833965Sjdp#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 185933965Sjdp#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xfffffffc 186033965Sjdp#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x2 186133965Sjdp#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xfffffffc 186233965Sjdp#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x2 186333965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 186433965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 186533965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 186633965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 186733965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 186860484Sobrien#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 186933965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 187033965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 187133965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 187233965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 187333965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 187433965Sjdp#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 187533965Sjdp#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 187633965Sjdp#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 187733965Sjdp#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 187833965Sjdp#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 187933965Sjdp#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1 188033965Sjdp#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 188133965Sjdp#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 188233965Sjdp#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 188333965Sjdp#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 188433965Sjdp#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 188533965Sjdp#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0xf0000 188633965Sjdp#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 188733965Sjdp#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x3ffffc 188833965Sjdp#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 188933965Sjdp#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x3ffffc 189033965Sjdp#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 189133965Sjdp#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xffffffe0 189233965Sjdp#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 189333965Sjdp#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xffffffff 189433965Sjdp#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 189533965Sjdp#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0xfffff 189633965Sjdp#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 189733965Sjdp#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 189833965Sjdp#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 189933965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1 190033965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 190133965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 190233965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 190333965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x4 190433965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 190533965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x8 190633965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 190733965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x70 190833965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 190933965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 191033965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 191133965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 191233965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 191333965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x200 191433965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 191533965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 191633965Sjdp#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 191733965Sjdp#define SDMA1_RLC0_DOORBELL__OFFSET_MASK 0x1fffff 191833965Sjdp#define SDMA1_RLC0_DOORBELL__OFFSET__SHIFT 0x0 191933965Sjdp#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000 192033965Sjdp#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 192133965Sjdp#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000 192260484Sobrien#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 192333965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1 192433965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__ATC__SHIFT 0x0 192533965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32_MASK 0x10 192678828Sobrien#define SDMA1_RLC0_VIRTUAL_ADDR__PTR32__SHIFT 0x4 192733965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 192833965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 192933965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 193033965Sjdp#define SDMA1_RLC0_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 193133965Sjdp#define SDMA1_RLC0_APE1_CNTL__BASE_MASK 0xffff 193233965Sjdp#define SDMA1_RLC0_APE1_CNTL__BASE__SHIFT 0x0 193333965Sjdp#define SDMA1_RLC0_APE1_CNTL__LIMIT_MASK 0xffff0000 193433965Sjdp#define SDMA1_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10 193533965Sjdp#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1 193633965Sjdp#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 193733965Sjdp#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xfffffffc 193833965Sjdp#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 193933965Sjdp#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0xfff 194033965Sjdp#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 194133965Sjdp#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 194233965Sjdp#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 194333965Sjdp#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 194433965Sjdp#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 194533965Sjdp#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xffffffff 194633965Sjdp#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 194733965Sjdp#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xffffffff 194833965Sjdp#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 194933965Sjdp#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x3fff 195033965Sjdp#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 195133965Sjdp#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1 195233965Sjdp#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 195333965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1 195433965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 195533965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x3e 195633965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 195733965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x200 195833965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 195933965Sjdp#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x1000 196033965Sjdp#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 196133965Sjdp#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x2000 196233965Sjdp#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 196333965Sjdp#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x1f0000 196433965Sjdp#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 196533965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x800000 196633965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 196733965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0xf000000 196833965Sjdp#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 196933965Sjdp#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xffffffff 197033965Sjdp#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 197133965Sjdp#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0xffffff 197233965Sjdp#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 197333965Sjdp#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xfffffffc 197433965Sjdp#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x2 197533965Sjdp#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xfffffffc 197633965Sjdp#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x2 197733965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1 197833965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 197933965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x2 198033965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 198133965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0xfff0 198233965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 198333965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 198433965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 198533965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xffffffff 198633965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 198733965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xfffffffc 198833965Sjdp#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 198960484Sobrien#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xffffffff 199033965Sjdp#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 199133965Sjdp#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xfffffffc 199233965Sjdp#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 199333965Sjdp#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1 199433965Sjdp#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 199533965Sjdp#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x10 199633965Sjdp#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 199733965Sjdp#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x100 199833965Sjdp#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 199933965Sjdp#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0xf0000 200033965Sjdp#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 200133965Sjdp#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x3ffffc 200233965Sjdp#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 200333965Sjdp#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x3ffffc 200433965Sjdp#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 200533965Sjdp#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xffffffe0 200633965Sjdp#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 200733965Sjdp#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xffffffff 200833965Sjdp#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 200933965Sjdp#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0xfffff 201033965Sjdp#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 201133965Sjdp#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x3fff 201233965Sjdp#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 201333965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1 201433965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 201533965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW_MASK 0x2 201633965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRE_CTXSW__SHIFT 0x1 201733965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x4 201833965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 201933965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x8 202033965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 202133965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x70 202233965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 202333965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x80 202433965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 202533965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x100 202633965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 202733965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x200 202833965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 202933965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x400 203033965Sjdp#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 203133965Sjdp#define SDMA1_RLC1_DOORBELL__OFFSET_MASK 0x1fffff 203233965Sjdp#define SDMA1_RLC1_DOORBELL__OFFSET__SHIFT 0x0 203333965Sjdp#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000 203433965Sjdp#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 203533965Sjdp#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000 203633965Sjdp#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 203733965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1 203833965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__ATC__SHIFT 0x0 203933965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32_MASK 0x10 204033965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__PTR32__SHIFT 0x4 204133965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE_MASK 0x700 204233965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__SHARED_BASE__SHIFT 0x8 204333965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE_MASK 0x40000000 204433965Sjdp#define SDMA1_RLC1_VIRTUAL_ADDR__VM_HOLE__SHIFT 0x1e 204533965Sjdp#define SDMA1_RLC1_APE1_CNTL__BASE_MASK 0xffff 204633965Sjdp#define SDMA1_RLC1_APE1_CNTL__BASE__SHIFT 0x0 204733965Sjdp#define SDMA1_RLC1_APE1_CNTL__LIMIT_MASK 0xffff0000 204833965Sjdp#define SDMA1_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10 204933965Sjdp#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1 205033965Sjdp#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 205133965Sjdp#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xfffffffc 205233965Sjdp#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 205333965Sjdp#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0xfff 205433965Sjdp#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 205533965Sjdp#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x1ff0000 205633965Sjdp#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 205733965Sjdp#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xfffffffc 205833965Sjdp#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 205933965Sjdp#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xffffffff 206033965Sjdp#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 206133965Sjdp#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xffffffff 206233965Sjdp#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 206333965Sjdp#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x3fff 206433965Sjdp#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 206533965Sjdp#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1 206633965Sjdp#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 206733965Sjdp#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT_MASK 0x7 206833965Sjdp#define HDP_HOST_PATH_CNTL__BIF_RDRET_CREDIT__SHIFT 0x0 206989857Sobrien#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT_MASK 0x1f8 207033965Sjdp#define HDP_HOST_PATH_CNTL__MC_WRREQ_CREDIT__SHIFT 0x3 207133965Sjdp#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x600 207233965Sjdp#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 207333965Sjdp#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x1800 207433965Sjdp#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 207533965Sjdp#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x180000 207633965Sjdp#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 207733965Sjdp#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x200000 207833965Sjdp#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 207933965Sjdp#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE_MASK 0x400000 208033965Sjdp#define HDP_HOST_PATH_CNTL__CACHE_INVALIDATE__SHIFT 0x16 208133965Sjdp#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK 0x800000 208233965Sjdp#define HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS__SHIFT 0x17 208333965Sjdp#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT_MASK 0xf000000 208433965Sjdp#define HDP_HOST_PATH_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x18 208533965Sjdp#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000 208633965Sjdp#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 208733965Sjdp#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000 208833965Sjdp#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 208933965Sjdp#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000 209033965Sjdp#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 209133965Sjdp#define HDP_NONSURFACE_BASE__NONSURF_BASE_MASK 0xffffffff 209233965Sjdp#define HDP_NONSURFACE_BASE__NONSURF_BASE__SHIFT 0x0 209333965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1 209433965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE__SHIFT 0x0 209533965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE_MASK 0x1e 209633965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1 209733965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN_MASK 0x60 209833965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_ENDIAN__SHIFT 0x5 209933965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE_MASK 0x380 210033965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_PIXEL_SIZE__SHIFT 0x7 210133965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM_MASK 0x1c00 210233965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_NUM__SHIFT 0xa 210333965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE_MASK 0x6000 210433965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_SAMPLE_SIZE__SHIFT 0xd 210533965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_PRIV_MASK 0x8000 210633965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_PRIV__SHIFT 0xf 210733965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT_MASK 0x10000 210833965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_TILE_COMPACT__SHIFT 0x10 210933965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT_MASK 0xe0000 211033965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_TILE_SPLIT__SHIFT 0x11 211133965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS_MASK 0x300000 211233965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_NUM_BANKS__SHIFT 0x14 211333965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH_MASK 0xc00000 211433965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_BANK_WIDTH__SHIFT 0x16 211533965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT_MASK 0x3000000 211633965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_BANK_HEIGHT__SHIFT 0x18 211733965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT_MASK 0xc000000 211833965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_MACRO_TILE_ASPECT__SHIFT 0x1a 211933965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE_MASK 0x70000000 212033965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_MICRO_TILE_MODE__SHIFT 0x1c 212133965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB_MASK 0x80000000 212233965Sjdp#define HDP_NONSURFACE_INFO__NONSURF_SLICE_TILE_MAX_MSB__SHIFT 0x1f 212333965Sjdp#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX_MASK 0x7ff 212433965Sjdp#define HDP_NONSURFACE_SIZE__NONSURF_PITCH_TILE_MAX__SHIFT 0x0 212533965Sjdp#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX_MASK 0xfffff800 212633965Sjdp#define HDP_NONSURFACE_SIZE__NONSURF_SLICE_TILE_MAX__SHIFT 0xb 212760484Sobrien#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1 212833965Sjdp#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 212933965Sjdp#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x2 213033965Sjdp#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 213133965Sjdp#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1 213233965Sjdp#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 213333965Sjdp#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x2 213433965Sjdp#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 213533965Sjdp#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xffffffff 213633965Sjdp#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 213733965Sjdp#define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 213833965Sjdp#define HDP_DEBUG1__HDP_DEBUG__SHIFT 0x0 213933965Sjdp#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x3f 214033965Sjdp#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 214133965Sjdp#define HDP_TILING_CONFIG__PIPE_TILING_MASK 0xe 214233965Sjdp#define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1 214333965Sjdp#define HDP_TILING_CONFIG__BANK_TILING_MASK 0x30 214433965Sjdp#define HDP_TILING_CONFIG__BANK_TILING__SHIFT 0x4 214533965Sjdp#define HDP_TILING_CONFIG__GROUP_SIZE_MASK 0xc0 214633965Sjdp#define HDP_TILING_CONFIG__GROUP_SIZE__SHIFT 0x6 214733965Sjdp#define HDP_TILING_CONFIG__ROW_TILING_MASK 0x700 214833965Sjdp#define HDP_TILING_CONFIG__ROW_TILING__SHIFT 0x8 214933965Sjdp#define HDP_TILING_CONFIG__BANK_SWAPS_MASK 0x3800 215033965Sjdp#define HDP_TILING_CONFIG__BANK_SWAPS__SHIFT 0xb 215133965Sjdp#define HDP_TILING_CONFIG__SAMPLE_SPLIT_MASK 0xc000 215233965Sjdp#define HDP_TILING_CONFIG__SAMPLE_SPLIT__SHIFT 0xe 215333965Sjdp#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS_MASK 0x7 215433965Sjdp#define HDP_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS__SHIFT 0x0 215533965Sjdp#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE_MASK 0x18 215633965Sjdp#define HDP_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE__SHIFT 0x3 215733965Sjdp#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0xff 215833965Sjdp#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 215933965Sjdp#define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0xff00 216033965Sjdp#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 216133965Sjdp#define HDP_ADDR_CONFIG__NUM_PIPES_MASK 0x7 216233965Sjdp#define HDP_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 216333965Sjdp#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 216433965Sjdp#define HDP_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 216533965Sjdp#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 216633965Sjdp#define HDP_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 216733965Sjdp#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 216833965Sjdp#define HDP_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 216933965Sjdp#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 217033965Sjdp#define HDP_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 217133965Sjdp#define HDP_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 217233965Sjdp#define HDP_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 217333965Sjdp#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 217433965Sjdp#define HDP_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 217533965Sjdp#define HDP_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 217633965Sjdp#define HDP_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 217733965Sjdp#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 217833965Sjdp#define HDP_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 217933965Sjdp#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1 218033965Sjdp#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 218133965Sjdp#define HDP_MISC_CNTL__VM_ID_MASK 0x1e 218233965Sjdp#define HDP_MISC_CNTL__VM_ID__SHIFT 0x1 218333965Sjdp#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x20 218433965Sjdp#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 218533965Sjdp#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x40 218633965Sjdp#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 218733965Sjdp#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT_MASK 0x780 218833965Sjdp#define HDP_MISC_CNTL__HDP_BIF_RDRET_CREDIT__SHIFT 0x7 218933965Sjdp#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x800 219033965Sjdp#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 219133965Sjdp#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR_MASK 0x1000 219233965Sjdp#define HDP_MISC_CNTL__NO_SPLIT_ARRAY_LINEAR__SHIFT 0xc 219333965Sjdp#define HDP_MISC_CNTL__MC_RDREQ_CREDIT_MASK 0x7e000 219433965Sjdp#define HDP_MISC_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 219533965Sjdp#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE_MASK 0x80000 219633965Sjdp#define HDP_MISC_CNTL__READ_CACHE_INVALIDATE__SHIFT 0x13 219733965Sjdp#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS_MASK 0x100000 219833965Sjdp#define HDP_MISC_CNTL__ADDRLIB_LINEAR_BYPASS__SHIFT 0x14 219933965Sjdp#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x200000 220033965Sjdp#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 220133965Sjdp#define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1 220233965Sjdp#define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 220333965Sjdp#define HDP_MEM_POWER_LS__LS_SETUP_MASK 0x7e 220433965Sjdp#define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1 220533965Sjdp#define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x1f80 220633965Sjdp#define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 220733965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI_MASK 0x7 220833965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_PRI__SHIFT 0x0 220933965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR_MASK 0x38 221033965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_DIR__SHIFT 0x3 221133965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM_MASK 0x1c0 221233965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_NUM__SHIFT 0x6 221333965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z_MASK 0xffe00 221433965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PREFETCH_MAX_Z__SHIFT 0x9 221533965Sjdp#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG_MASK 0xf8000000 2216#define HDP_NONSURFACE_PREFETCH__NONSURF_PIPE_CONFIG__SHIFT 0x1b 2217#define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1 2218#define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 2219#define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x2 2220#define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 2221#define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x3c 2222#define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 2223#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x40 2224#define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 2225#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x80 2226#define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 2227#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x3f00 2228#define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 2229#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x4000 2230#define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 2231#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x8000 2232#define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 2233#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xffffffff 2234#define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 2235#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1 2236#define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 2237#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x2 2238#define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 2239#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x4 2240#define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 2241#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x8 2242#define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 2243#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xffffffff 2244#define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 2245#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xffffffff 2246#define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 2247#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xffffffff 2248#define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 2249#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0xf 2250#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 2251#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0xf0 2252#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 2253#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x700 2254#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 2255#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0xf800 2256#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 2257#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x10000 2258#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 2259#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE_MASK 0x20000 2260#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_SIDE__SHIFT 0x11 2261#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x40000 2262#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 2263#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x80000 2264#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 2265#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x100000 2266#define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 2267#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0xffff 2268#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 2269#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0xf0000 2270#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 2271#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x700000 2272#define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 2273#define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xffffffff 2274#define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 2275#define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xffffffff 2276#define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 2277#define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xffffffff 2278#define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 2279#define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xffffffff 2280#define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 2281#define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xffffffff 2282#define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 2283#define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xffffffff 2284#define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 2285#define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xffffffff 2286#define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 2287#define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xffffffff 2288#define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 2289#define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xffffffff 2290#define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 2291#define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xffffffff 2292#define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 2293#define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xffffffff 2294#define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 2295#define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xffffffff 2296#define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 2297#define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xffffffff 2298#define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 2299#define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xffffffff 2300#define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 2301#define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xffffffff 2302#define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 2303#define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xffffffff 2304#define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 2305#define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xffffffff 2306#define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 2307#define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xffffffff 2308#define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 2309#define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xffffffff 2310#define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 2311#define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xffffffff 2312#define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 2313#define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xffffffff 2314#define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 2315#define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xffffffff 2316#define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 2317#define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xffffffff 2318#define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 2319#define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xffffffff 2320#define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 2321#define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xffffffff 2322#define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 2323#define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xffffffff 2324#define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 2325#define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xffffffff 2326#define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 2327#define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xffffffff 2328#define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 2329#define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xffffffff 2330#define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 2331#define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xffffffff 2332#define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 2333#define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xffffffff 2334#define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 2335#define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xffffffff 2336#define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 2337#define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xffffffff 2338#define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 2339#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0xf 2340#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 2341#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x30 2342#define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 2343#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x3fff 2344#define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 2345#define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1 2346#define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 2347#define HDP_XDP_P2P_MBX_ADDR0__ADDR_MASK 0x1ffffe 2348#define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1 2349#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x1e00000 2350#define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x15 2351#define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1 2352#define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 2353#define HDP_XDP_P2P_MBX_ADDR1__ADDR_MASK 0x1ffffe 2354#define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1 2355#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x1e00000 2356#define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x15 2357#define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1 2358#define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 2359#define HDP_XDP_P2P_MBX_ADDR2__ADDR_MASK 0x1ffffe 2360#define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1 2361#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x1e00000 2362#define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x15 2363#define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1 2364#define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 2365#define HDP_XDP_P2P_MBX_ADDR3__ADDR_MASK 0x1ffffe 2366#define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1 2367#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x1e00000 2368#define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x15 2369#define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1 2370#define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 2371#define HDP_XDP_P2P_MBX_ADDR4__ADDR_MASK 0x1ffffe 2372#define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1 2373#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x1e00000 2374#define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x15 2375#define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1 2376#define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 2377#define HDP_XDP_P2P_MBX_ADDR5__ADDR_MASK 0x1ffffe 2378#define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1 2379#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x1e00000 2380#define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x15 2381#define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1 2382#define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 2383#define HDP_XDP_P2P_MBX_ADDR6__ADDR_MASK 0x1ffffe 2384#define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1 2385#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x1e00000 2386#define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x15 2387#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1 2388#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV__SHIFT 0x0 2389#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x6 2390#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1 2391#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN_MASK 0x8 2392#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_TRAN__SHIFT 0x3 2393#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0xf0 2394#define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x4 2395#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1 2396#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV__SHIFT 0x0 2397#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP_MASK 0x6 2398#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1 2399#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN_MASK 0x8 2400#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_TRAN__SHIFT 0x3 2401#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV_MASK 0x10 2402#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_PRIV__SHIFT 0x4 2403#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP_MASK 0x60 2404#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_SWAP__SHIFT 0x5 2405#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN_MASK 0x80 2406#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_TRAN__SHIFT 0x7 2407#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE_MASK 0x3f00 2408#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE__SHIFT 0x8 2409#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0xfc000 2410#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 2411#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK_MASK 0x700000 2412#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK__SHIFT 0x14 2413#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID_MASK 0x7800000 2414#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_VMID__SHIFT 0x17 2415#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID_MASK 0x78000000 2416#define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_SID_TAP_WRREQ_VMID__SHIFT 0x1b 2417#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1 2418#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 2419#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x6 2420#define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 2421#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1 2422#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN__SHIFT 0x0 2423#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER_MASK 0x6 2424#define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1 2425#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL_MASK 0x18 2426#define HDP_XDP_SID_CFG__SID_CFG_FLNUM_MSB_SEL__SHIFT 0x3 2427#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x3f 2428#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 2429#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0xfc0 2430#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 2431#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x1000 2432#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 2433#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x2000 2434#define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 2435#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT_MASK 0x3f 2436#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_ENABLE_COUNT__SHIFT 0x0 2437#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS_MASK 0x40 2438#define HDP_XDP_SRBM_CFG__SRBM_CFG_REG_CLK_GATING_DIS__SHIFT 0x6 2439#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK_MASK 0x80 2440#define HDP_XDP_SRBM_CFG__SRBM_CFG_WAKE_DYN_CLK__SHIFT 0x7 2441#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY_MASK 0xf 2442#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_0_ON_DELAY__SHIFT 0x0 2443#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY_MASK 0xff0 2444#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_1_OFF_DELAY__SHIFT 0x4 2445#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD_MASK 0x3ffff000 2446#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_2_RSVD__SHIFT 0xc 2447#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE_MASK 0x40000000 2448#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE__SHIFT 0x1e 2449#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE_MASK 0x80000000 2450#define HDP_XDP_CGTT_BLK_CTRL__CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE__SHIFT 0x1f 2451#define HDP_XDP_P2P_BAR0__ADDR_MASK 0xffff 2452#define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 2453#define HDP_XDP_P2P_BAR0__FLUSH_MASK 0xf0000 2454#define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 2455#define HDP_XDP_P2P_BAR0__VALID_MASK 0x100000 2456#define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 2457#define HDP_XDP_P2P_BAR1__ADDR_MASK 0xffff 2458#define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 2459#define HDP_XDP_P2P_BAR1__FLUSH_MASK 0xf0000 2460#define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 2461#define HDP_XDP_P2P_BAR1__VALID_MASK 0x100000 2462#define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 2463#define HDP_XDP_P2P_BAR2__ADDR_MASK 0xffff 2464#define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 2465#define HDP_XDP_P2P_BAR2__FLUSH_MASK 0xf0000 2466#define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 2467#define HDP_XDP_P2P_BAR2__VALID_MASK 0x100000 2468#define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 2469#define HDP_XDP_P2P_BAR3__ADDR_MASK 0xffff 2470#define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 2471#define HDP_XDP_P2P_BAR3__FLUSH_MASK 0xf0000 2472#define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 2473#define HDP_XDP_P2P_BAR3__VALID_MASK 0x100000 2474#define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 2475#define HDP_XDP_P2P_BAR4__ADDR_MASK 0xffff 2476#define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 2477#define HDP_XDP_P2P_BAR4__FLUSH_MASK 0xf0000 2478#define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 2479#define HDP_XDP_P2P_BAR4__VALID_MASK 0x100000 2480#define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 2481#define HDP_XDP_P2P_BAR5__ADDR_MASK 0xffff 2482#define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 2483#define HDP_XDP_P2P_BAR5__FLUSH_MASK 0xf0000 2484#define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 2485#define HDP_XDP_P2P_BAR5__VALID_MASK 0x100000 2486#define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 2487#define HDP_XDP_P2P_BAR6__ADDR_MASK 0xffff 2488#define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 2489#define HDP_XDP_P2P_BAR6__FLUSH_MASK 0xf0000 2490#define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 2491#define HDP_XDP_P2P_BAR6__VALID_MASK 0x100000 2492#define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 2493#define HDP_XDP_P2P_BAR7__ADDR_MASK 0xffff 2494#define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 2495#define HDP_XDP_P2P_BAR7__FLUSH_MASK 0xf0000 2496#define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 2497#define HDP_XDP_P2P_BAR7__VALID_MASK 0x100000 2498#define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 2499#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xffffffff 2500#define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 2501#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x3ffffff 2502#define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 2503#define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x3ffff 2504#define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 2505#define HDP_XDP_STICKY__STICKY_STS_MASK 0xffff 2506#define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 2507#define HDP_XDP_STICKY__STICKY_W1C_MASK 0xffff0000 2508#define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 2509#define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0xff 2510#define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 2511#define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0xff00 2512#define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 2513#define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0xff0000 2514#define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 2515#define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xff000000 2516#define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 2517#define HDP_XDP_DBG_ADDR__STS_MASK 0xffff 2518#define HDP_XDP_DBG_ADDR__STS__SHIFT 0x0 2519#define HDP_XDP_DBG_ADDR__CTRL_MASK 0xffff0000 2520#define HDP_XDP_DBG_ADDR__CTRL__SHIFT 0x10 2521#define HDP_XDP_DBG_DATA__STS_MASK 0xffff 2522#define HDP_XDP_DBG_DATA__STS__SHIFT 0x0 2523#define HDP_XDP_DBG_DATA__CTRL_MASK 0xffff0000 2524#define HDP_XDP_DBG_DATA__CTRL__SHIFT 0x10 2525#define HDP_XDP_DBG_MASK__STS_MASK 0xffff 2526#define HDP_XDP_DBG_MASK__STS__SHIFT 0x0 2527#define HDP_XDP_DBG_MASK__CTRL_MASK 0xffff0000 2528#define HDP_XDP_DBG_MASK__CTRL__SHIFT 0x10 2529#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0xf 2530#define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 2531#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0xf0 2532#define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 2533#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0xf00 2534#define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 2535#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0xf000 2536#define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 2537#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0xf0000 2538#define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 2539#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0xf00000 2540#define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 2541#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0xf000000 2542#define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 2543#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xf0000000 2544#define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 2545 2546#endif /* OSS_2_4_SH_MASK_H */ 2547