Searched refs:xa (Results 226 - 250 of 1008) sorted by relevance

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/netbsd-current/external/gpl3/gdb.old/dist/ld/testsuite/ld-m68hc11/
H A Dadj-jump.d17 0+8022 <L1\+0xa> bne 0x0+8018 <L1>
57 0+8072 <L2\+0xa> addd \*0x0+4 <_toto>
H A Dfar-hc11.d21 0+801e <_start\+0xa> ldx \#0x0+5678 .*
54 0+8060 <__far_trampoline\+0xa> pulx
/netbsd-current/external/gpl3/gdb.old/dist/include/opcode/
H A Dcsky.h74 #define CSKY_ARCH_801 0xa
/netbsd-current/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.dwarf2/
H A Ddw2-op-stack-value.S127 .uleb128 0xa /* DW_FORM_block1 */
H A Dcallframecfa.S203 .uleb128 0xa
220 .uleb128 0xa
246 .uleb128 0xa
/netbsd-current/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Dstk2.s107 .dw 0xa
/netbsd-current/sys/arch/newsmips/dev/
H A Ddmac_0448.h61 #define DMAC_COFSH (DMAC_BASE + 0xa)
/netbsd-current/sys/arch/m68k/include/
H A Dmmu_51.h228 #define TCR51_PS_1K __SHIFTIN(0xa, TCR51_PS)
/netbsd-current/bin/ed/
H A Dsub.c129 long xa = current_addr; local
160 xa = current_addr;
163 current_addr = xa;
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_0_0_sh_mask.h65 #define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
137 #define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
164 #define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT 0xa
306 #define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT 0xa
326 #define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT 0xa
446 #define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT 0xa
573 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT 0xa
619 #define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT 0xa
696 #define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT 0xa
768 #define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0xa
[all...]
/netbsd-current/sys/arch/bebox/stand/boot/
H A Dvreset.c88 { 0x3d4, 0xa, 0x0d },
133 { 0x3d4, 0xa, 0x0d },
246 { 0x1e, 0xa, 0x38 },
254 { 0xd, 0xa, 0x10 },
284 { 0x1, 0xa, 0x3d },
292 { 0x1e, 0x2f, 0xa },
372 { 0xa, 0x8, 0x10 },
378 { 0x10, 0x8, 0xa },
380 { 0x10, 0xa, 0x8 },
386 { 0xa,
[all...]
/netbsd-current/external/gpl3/gdb/dist/gdb/testsuite/gdb.dwarf2/
H A Dcallframecfa.S203 .uleb128 0xa
220 .uleb128 0xa
246 .uleb128 0xa
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_sh_mask.h45 #define PSWUSCFG0_COMMAND__INT_DIS__SHIFT 0xa
232 #define PSWUSCFG0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
302 #define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
334 #define PSWUSCFG0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
363 #define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
398 #define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
427 #define PSWUSCFG0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
460 #define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
571 #define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
809 #define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
[all...]
H A Dnbio_7_0_sh_mask.h126 #define NB_NBCFG0_NB_PCI_ARB__PMETOAckStatus__SHIFT 0xa
235 #define IOMMU_L2_0_IOMMU_COMMAND__INTERRUPT_DIS__SHIFT 0xa
435 #define IOMMU_L2_0_IOMMU_CONTROL_W__MSI_MULT_MESS_CAP_W__SHIFT 0xa
454 #define IOMMU_L2_0_IOMMU_MMIO_CONTROL0_W__HATS_W__SHIFT 0xa
486 #define IOMMU_L2_0_IOMMU_MMIO_CONTROL1_W__BLOCK_STOPMARK_SUP_W__SHIFT 0xa
565 #define IOMMU_L2_0_SMMU_MMIO_IDR0_W__ATS_W__SHIFT 0xa
628 #define IOMMU_L2_0_SMMU_MMIO_IDR2_W__BA_RAS_W__SHIFT 0xa
679 #define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa
857 #define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
927 #define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h71 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa
104 #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa
143 #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
168 #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
224 #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa
289 #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa
361 #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
426 #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
496 #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa
553 #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h74 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa
107 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa
146 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
171 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa
227 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa
292 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa
362 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
421 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa
491 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa
548 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_3_0_1_sh_mask.h102 #define IH_CNTL__MC_FIFO_HIGHWATER__SHIFT 0xa
140 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa
152 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0xa
190 #define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa
230 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa
336 #define SRBM_STATUS2__SDMA2_BUSY__SHIFT 0xa
372 #define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
416 #define SRBM_STATUS3__MCD2_BUSY__SHIFT 0xa
446 #define SRBM_SOFT_RESET__SOFT_RESET_IH__SHIFT 0xa
556 #define SRBM_DEBUG__ISP_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xa
[all...]
H A Doss_3_0_1_enum.h66 IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
108 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0xa,
283 SRBM_PERF_SEL_SEM_BUSY = 0xa,
313 GRBM_GFX_INDEX_VP8 = 0xa,
330 SRBM_GFX_CNTL_VP8 = 0xa,
347 SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
436 DBG_BLOCK_ID_IH = 0xa,
693 DBG_BLOCK_ID_VC0_BY2 = 0xa,
815 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
877 DBG_BLOCK_ID_SXS_BY8 = 0xa,
[all...]
H A Doss_3_0_enum.h66 IH_PERF_SEL_CLIENT7_IH_STALL = 0xa,
218 SRBM_PERF_SEL_SEM_BUSY = 0xa,
248 GRBM_GFX_INDEX_SAMSCP = 0xa,
265 SRBM_GFX_CNTL_SAMSCP = 0xa,
282 SDMA_PERF_SEL_RB_CMD_FULL = 0xa,
345 ARRAY_PRT_2D_TILED_THICK = 0xa,
443 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
603 DBG_BLOCK_ID_IH = 0xa,
837 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
955 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h62 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
112 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
234 #define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
264 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
344 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
422 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
462 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
508 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
534 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
552 #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
[all...]
H A Dgmc_8_1_enum.h46 ARRAY_PRT_2D_TILED_THICK = 0xa,
144 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
304 DBG_BLOCK_ID_IH = 0xa,
538 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
656 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
716 DBG_BLOCK_ID_CB00_BY8 = 0xa,
747 DBG_BLOCK_ID_TA00_BY16 = 0xa,
804 CMASK_ALPHA1_FRAG4 = 0xa,
840 COLOR_8_8_8_8 = 0xa,
866 FMT_8_8_8_8 = 0xa,
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_enum.h46 ARRAY_PRT_2D_TILED_THICK = 0xa,
144 DBG_CLIENT_BLKID_uvdm_1 = 0xa,
268 DBG_BLOCK_ID_IH = 0xa,
502 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
620 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
680 DBG_BLOCK_ID_CB00_BY8 = 0xa,
711 DBG_BLOCK_ID_TA00_BY16 = 0xa,
762 CMASK_ALPHA1_FRAG4 = 0xa,
798 COLOR_8_8_8_8 = 0xa,
824 FMT_8_8_8_8 = 0xa,
[all...]
H A Ddce_10_0_enum.h40 DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
92 DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
110 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
430 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa,
468 DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
621 ARRAY_PRT_2D_TILED_THICK = 0xa,
719 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
879 DBG_BLOCK_ID_IH = 0xa,
1113 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
1231 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_enum.h46 ARRAY_PRT_2D_TILED_THICK = 0xa,
144 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
304 DBG_BLOCK_ID_IH = 0xa,
538 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
656 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
716 DBG_BLOCK_ID_CB00_BY8 = 0xa,
747 DBG_BLOCK_ID_TA00_BY16 = 0xa,
804 CMASK_ALPHA1_FRAG4 = 0xa,
840 COLOR_8_8_8_8 = 0xa,
866 FMT_8_8_8_8 = 0xa,
[all...]
/netbsd-current/sys/dev/ic/
H A Dmlxvar.h228 mc->mc_mbox[0xa] = (f4 >> 16);
248 mc->mc_mbox[0xa] = (f7 >> 16);
268 mc->mc_mbox[0xa] = (f6 >> 16);
287 mc->mc_mbox[0xa] = (f3 >> 16);
306 mc->mc_mbox[0xa] = (f4 >> 16);

Completed in 8976 milliseconds

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