Searched refs:SIM_CPU (Results 76 - 100 of 357) sorted by relevance

1234567891011>>

/netbsd-current/external/gpl3/gdb.old/dist/sim/common/
H A Dcgen-trace.h23 void cgen_trace_insn_init (SIM_CPU *, int);
24 void cgen_trace_insn_fini (SIM_CPU *, const struct argbuf *, int);
25 void cgen_trace_insn (SIM_CPU *, const struct cgen_insn *,
27 void cgen_trace_extract (SIM_CPU *, IADDR, char *, ...);
28 void cgen_trace_result (SIM_CPU *, char *, int, ...);
29 void cgen_trace_printf (SIM_CPU *, char *fmt, ...);
/netbsd-current/external/gpl3/gdb/dist/sim/common/
H A Dcgen-trace.h25 void cgen_trace_insn_init (SIM_CPU *, int);
26 void cgen_trace_insn_fini (SIM_CPU *, const struct argbuf *, int);
27 void cgen_trace_insn (SIM_CPU *, const struct cgen_insn *,
29 void cgen_trace_extract (SIM_CPU *, IADDR, const char *, ...);
30 void cgen_trace_result (SIM_CPU *, const char *, int, ...);
31 void cgen_trace_printf (SIM_CPU *, const char *fmt, ...) ATTRIBUTE_PRINTF_2;
/netbsd-current/external/gpl3/gdb/dist/sim/cris/
H A Ddecodev32.h27 extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
30 extern void crisv32f_init_idesc_table (SIM_CPU *);
31 extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
32 extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
33 extern void crisv32f_specific_init (SIM_CPU *);
126 extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
127 extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
128 extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
129 extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
130 extern int crisv32f_model_crisv32_u_stall (SIM_CPU *, cons
[all...]
H A Dcris-tmpl.c38 MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
81 MY (f_fetch_register) (SIM_CPU *current_cpu, int rn, void *buf,
92 MY (f_store_register) (SIM_CPU *current_cpu, int rn, const void *buf,
109 MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
178 MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
206 MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
217 MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
224 MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
230 MY (f_model_mark_get_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
236 MY (f_model_mark_set_h_gr) (SIM_CPU *current_cp
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/sim/cris/
H A Ddecodev32.h27 extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
30 extern void crisv32f_init_idesc_table (SIM_CPU *);
31 extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
32 extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
125 extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
126 extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
127 extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
128 extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
129 extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
130 extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, cons
[all...]
H A Dcris-tmpl.c33 MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
76 MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
87 MY (f_store_register) (SIM_CPU *current_cpu, int rn,
104 MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
173 MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
200 MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
211 MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
219 MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
225 MY (f_model_mark_get_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
231 MY (f_model_mark_set_h_gr) (SIM_CPU *current_cp
[all...]
H A Dcris-sim.h82 extern USI cris_bmod_handler (SIM_CPU *, UINT, USI);
83 extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
84 extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
85 extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
86 extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI,
93 extern int crisv10deliver_interrupt (SIM_CPU *,
96 extern int crisv32deliver_interrupt (SIM_CPU *,
/netbsd-current/external/gpl3/gdb.old/dist/sim/m32r/
H A Dm32rx.c30 m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
38 m32rxf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
48 m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
83 m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
149 m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
155 m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
164 m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
175 m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
183 m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
199 m32rxf_h_accums_set_handler (SIM_CPU *current_cp
[all...]
H A Dm32r2.c30 m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
38 m32r2f_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
48 m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
83 m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
149 m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)
155 m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
164 m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)
175 m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
183 m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
199 m32r2f_h_accums_set_handler (SIM_CPU *current_cp
[all...]
/netbsd-current/external/gpl3/gdb/dist/sim/m32r/
H A Dm32r2.c33 m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len)
41 m32r2f_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len)
51 m32r2f_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
86 m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
152 m32r2f_h_psw_get_handler (SIM_CPU *current_cpu)
158 m32r2f_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
167 m32r2f_h_accum_get_handler (SIM_CPU *current_cpu)
178 m32r2f_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
186 m32r2f_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
202 m32r2f_h_accums_set_handler (SIM_CPU *current_cp
[all...]
H A Dm32rx.c33 m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len)
41 m32rxf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len)
51 m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
86 m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
152 m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
158 m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
167 m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
178 m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
186 m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
202 m32rxf_h_accums_set_handler (SIM_CPU *current_cp
[all...]
/netbsd-current/external/gpl3/gdb/dist/sim/iq2000/
H A Diq2000.c42 fetch_str (SIM_CPU *current_cpu, PCADDR pc, DI addr)
55 do_syscall (SIM_CPU *current_cpu, PCADDR pc)
136 do_break (SIM_CPU *current_cpu, PCADDR pc)
145 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
157 iq2000_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
171 iq2000bf_model_insn_before (SIM_CPU *cpu, int first_p)
183 iq2000bf_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
190 iq2000bf_model_iq2000_u_exec (SIM_CPU *cpu, const IDESC *idesc,
197 get_h_pc (SIM_CPU *cpu)
203 set_h_pc (SIM_CPU *cp
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/sim/frv/
H A Dprofile-fr450.c34 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
41 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
52 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
78 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
105 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
116 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
127 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
137 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
147 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
180 frvbf_model_fr450_u_gr_store (SIM_CPU *cp
[all...]
/netbsd-current/external/gpl3/gdb/dist/sim/frv/
H A Dprofile-fr450.c36 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
43 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
54 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
80 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
107 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
118 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
129 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
139 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
149 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
182 frvbf_model_fr450_u_gr_store (SIM_CPU *cp
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/sim/sh64/
H A Dsh64.c50 sh64_endian (SIM_CPU *current_cpu)
56 sh64_fldi0 (SIM_CPU *current_cpu)
64 sh64_fldi1 (SIM_CPU *current_cpu)
72 sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
84 sh64_fabss(SIM_CPU *current_cpu, SF frgh)
96 sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
109 sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
122 sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
132 sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
142 sh64_fcmpged(SIM_CPU *current_cp
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/sim/bfin/
H A Ddv-bfin_mmu.h24 void mmu_check_addr (SIM_CPU *, bu32 addr, bool write, bool inst, int size);
25 void mmu_check_cache_addr (SIM_CPU *, bu32 addr, bool write, bool inst);
26 void mmu_process_fault (SIM_CPU *, bu32 addr, bool write, bool inst, bool unaligned, bool miss);
27 void mmu_log_ifault (SIM_CPU *);
H A Ddv-bfin_trace.h32 void bfin_trace_queue (SIM_CPU *, bu32 src_pc, bu32 dst_pc, int hwloop);
/netbsd-current/external/gpl3/gdb/dist/sim/bfin/
H A Ddv-bfin_mmu.h26 void mmu_check_addr (SIM_CPU *, bu32 addr, bool write, bool inst, int size);
27 void mmu_check_cache_addr (SIM_CPU *, bu32 addr, bool write, bool inst);
28 void mmu_process_fault (SIM_CPU *, bu32 addr, bool write, bool inst, bool unaligned, bool miss);
29 void mmu_log_ifault (SIM_CPU *);
H A Ddv-bfin_trace.h32 void bfin_trace_queue (SIM_CPU *, bu32 src_pc, bu32 dst_pc, int hwloop);
/netbsd-current/external/gpl3/gdb/dist/sim/riscv/
H A Dmachs.c27 riscv_model_init (SIM_CPU *cpu)
32 riscv_init_cpu (SIM_CPU *cpu)
37 riscv_prepare_run (SIM_CPU *cpu)
43 sizeof (SIM_CPU),
/netbsd-current/external/gpl3/gdb.old/dist/sim/bpf/
H A Ddecode-be.h28 extern const IDESC *bpfbf_ebpfbe_decode (SIM_CPU *, IADDR,
31 extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *);
32 extern void bpfbf_ebpfbe_sem_init_idesc_table (SIM_CPU *);
33 extern void bpfbf_ebpfbe_semf_init_idesc_table (SIM_CPU *);
87 extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
91 extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
92 extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
H A Ddecode-le.h28 extern const IDESC *bpfbf_ebpfle_decode (SIM_CPU *, IADDR,
31 extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *);
32 extern void bpfbf_ebpfle_sem_init_idesc_table (SIM_CPU *);
33 extern void bpfbf_ebpfle_semf_init_idesc_table (SIM_CPU *);
87 extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
91 extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
92 extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
/netbsd-current/external/gpl3/gdb.old/dist/sim/iq2000/
H A Ddecode.h27 extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR,
30 extern void iq2000bf_init_idesc_table (SIM_CPU *);
31 extern void iq2000bf_sem_init_idesc_table (SIM_CPU *);
32 extern void iq2000bf_semf_init_idesc_table (SIM_CPU *);
90 extern int iq2000bf_model_iq2000_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
94 extern void iq2000bf_model_insn_before (SIM_CPU *, int /*first_p*/);
95 extern void iq2000bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
/netbsd-current/external/gpl3/gdb/dist/sim/bpf/
H A Ddecode-be.h28 extern const IDESC *bpfbf_ebpfbe_decode (SIM_CPU *, IADDR,
31 extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *);
32 extern void bpfbf_ebpfbe_sem_init_idesc_table (SIM_CPU *);
33 extern void bpfbf_ebpfbe_semf_init_idesc_table (SIM_CPU *);
87 extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
91 extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
92 extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
H A Ddecode-le.h28 extern const IDESC *bpfbf_ebpfle_decode (SIM_CPU *, IADDR,
31 extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *);
32 extern void bpfbf_ebpfle_sem_init_idesc_table (SIM_CPU *);
33 extern void bpfbf_ebpfle_semf_init_idesc_table (SIM_CPU *);
87 extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
91 extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
92 extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);

Completed in 305 milliseconds

1234567891011>>