Lines Matching refs:SIM_CPU
33 m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len)
41 m32rxf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len)
51 m32rxf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
86 m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
152 m32rxf_h_psw_get_handler (SIM_CPU *current_cpu)
158 m32rxf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
167 m32rxf_h_accum_get_handler (SIM_CPU *current_cpu)
178 m32rxf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
186 m32rxf_h_accums_get_handler (SIM_CPU *current_cpu, UINT regno)
202 m32rxf_h_accums_set_handler (SIM_CPU *current_cpu, UINT regno, DI newval)
219 m32rxf_model_insn_before (SIM_CPU *cpu, int first_p)
230 m32rxf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
236 check_load_stall (SIM_CPU *cpu, int regno)
250 m32rxf_model_m32rx_u_exec (SIM_CPU *cpu, const IDESC *idesc,
260 m32rxf_model_m32rx_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
270 m32rxf_model_m32rx_u_mac (SIM_CPU *cpu, const IDESC *idesc,
280 m32rxf_model_m32rx_u_cti (SIM_CPU *cpu, const IDESC *idesc,
299 m32rxf_model_m32rx_u_load (SIM_CPU *cpu, const IDESC *idesc,
308 m32rxf_model_m32rx_u_store (SIM_CPU *cpu, const IDESC *idesc,