Searched refs:RegNum (Results 26 - 45 of 45) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp346 unsigned RegNum = TRI->getEncodingValue(Reg); local
351 FPUBitmask |= (1 << RegNum);
354 FPUBitmask |= (3 << RegNum);
358 CPUBitmask |= (1 << RegNum);
H A DMipsSEISelDAGToDAG.cpp79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); local
80 return Mips::MSACtrlRegClass.getRegister(RegNum);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1234 unsigned &RegNum, unsigned &RegWidth,
1237 unsigned &RegNum, unsigned &RegWidth,
1239 unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1242 unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1245 unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1249 unsigned RegNum,
2434 unsigned RegNum,
2447 if (RegNum % AlignSize != 0) {
2452 unsigned RegIdx = RegNum / AlignSize;
2513 unsigned &RegNum, unsigne
2433 getRegularReg(RegisterKind RegKind, unsigned RegNum, unsigned RegWidth, SMLoc Loc) argument
2512 ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2527 ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2561 ParseRegList(RegisterKind &RegKind, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2615 ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, unsigned &RegNum, unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens) argument
2647 ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, unsigned &RegNum, unsigned &RegWidth, bool RestoreOnFailure ) argument
2718 unsigned Reg, RegNum, RegWidth; local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp270 MCRegister RegNum; member in struct:__anon2586::RISCVOperand::RegOp
328 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
337 RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
708 return Reg.RegNum.id();
773 Op->Reg.RegNum = RegNo;
936 Op.Reg.RegNum = convertFPR64ToFPR32(Reg);
942 Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
948 Op.Reg.RegNum = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind);
949 if (Op.Reg.RegNum == 0)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp826 unsigned RegNum; member in struct:__anon2324::ARMOperand::RegOp
831 unsigned RegNum; member in struct:__anon2324::ARMOperand::VectorListOp
860 unsigned RegNum; member in struct:__anon2324::ARMOperand::PostIdxRegOp
966 return Reg.RegNum;
1446 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);
2029 VectorList.RegNum);
2035 .contains(VectorList.RegNum));
2052 .contains(VectorList.RegNum));
2068 VectorList.RegNum);
2087 .contains(VectorList.RegNum));
2476 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local
2483 unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; local
2490 unsigned RegNum; local
3612 CreateCCOut(unsigned RegNum, SMLoc S) argument
3629 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument
3746 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
3760 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
3772 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
3821 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
4082 unsigned RegNum = MatchRegisterName(lowerCase); local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.cpp271 static const char *getRegisterName(unsigned RegNum) { argument
632 for (; Entry->Num && Entry->Num != RegNum; ++Entry)
/netbsd-current/external/apache2/llvm/dist/llvm/tools/llvm-cfi-verify/lib/
H A DFileAnalysis.cpp343 unsigned RegNum = *RI; local
344 if (InstrDesc.hasDefOfPhysReg(NodeInstr.Instruction, RegNum,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp2428 unsigned RegNum;
2436 RegNum = RegLst & 0xf;
2439 if (RegNum > 9)
2442 for (unsigned i = 0; i < RegNum; i++)
2465 unsigned RegNum = RegLst & 0x3; local
2467 for (unsigned i = 0; i <= RegNum; i++)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp406 unsigned RegNum = MRI->getDwarfRegNum(Reg, true); local
408 MCCFIInstruction::createDefCfaRegister(nullptr, RegNum));
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp206 int RegNum, const DebugLoc &DL);
480 int RegNum, const DebugLoc &DL) {
485 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
478 insertCondBranchBefore( MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, const DebugLoc &DL) argument
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1624 unsigned RegNum = Reg.EnumValue; local
1625 if (AllocatableRegs.count(RegNum))
1628 UberSetIDs.join(0, RegNum);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1100 if (unsigned RegNum = MO2.getReg()) {
1102 printRegName(O, RegNum);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp289 unsigned RegNum = RegMap[Reg]; local
315 Ret |= (RegNum & 0x0FFFFFFF);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1069 unsigned RegNum = MO.isUndef() ? std::numeric_limits<unsigned>::max() local
1074 if (RegNum <= PRegNum)
1079 else if (!isNotVFP && RegNum != PRegNum+1)
1098 PRegNum = RegNum;
/netbsd-current/external/apache2/llvm/dist/clang/include/clang/Basic/
H A DTargetInfo.h1123 const unsigned RegNum; member in struct:clang::TargetInfo::AddlRegName
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1269 unsigned RegNum = MRI->getDwarfRegNum(Reg, true);
1271 MCCFIInstruction::createDefCfaRegister(nullptr, RegNum));
1278 unsigned RegNum = MRI->getDwarfRegNum(Reg, true);
1280 MCCFIInstruction::cfiDefCfa(nullptr, RegNum, Offset));
H A DPPCISelLowering.cpp15680 int RegNum = atoi(Constraint.data() + 2); local
15681 if (RegNum > 31 || RegNum < 0)
15685 ? std::make_pair(PPC::R0 + RegNum, &PPC::GPRCRegClass)
15686 : std::make_pair(PPC::F0 + RegNum, &PPC::F4RCRegClass);
15689 ? std::make_pair(PPC::S0 + RegNum, &PPC::SPERCRegClass)
15690 : std::make_pair(PPC::F0 + RegNum, &PPC::F8RCRegClass);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp145 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
147 // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
148 if (RegNum != NumArgRegs && RegNum % 2 == 1)
149 State.AllocateReg(ArgRegs[RegNum]);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1799 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1800 return X86ATTInstPrinter::getRegisterName(RegNum);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp6687 int64_t RegNum = Token.getIntVal(); local
6688 if (RegNum < 0 || RegNum > 31) {
6695 RegNum, Token.getString(), getContext().getRegisterInfo(), S,

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