/netbsd-current/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
H A D | c_dsp32mult_dr_ih.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IH); 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IH); 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IH); 67 R1.H = R4.H * R5.L, R1.L = R4 [all...] |
H A D | c_dsp32mult_dr_is.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2); 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2); 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2); 67 R1.H = R4.H * R5.L, R1.L = R4 [all...] |
H A D | c_dsp32mult_dr_iu.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (IU); 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (IU); 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (IU); 67 R1.H = R4.H * R5.L, R1.L = R4 [all...] |
H A D | c_dsp32mult_dr_s.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (S2RND); 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (S2RND); 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (S2RND); 67 R1.H = R4.H * R5.L, R1.L = R4 [all...] |
H A D | c_dsp32mult_dr_tu.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (TFU); 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (TFU); 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (TFU); 67 R1.H = R4.H * R5.L, R1.L = R4 [all...] |
H A D | c_dsp32mult_dr_u.s | 16 R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (FU); 41 R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (FU); 66 R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (FU); 67 R1.H = R4.H * R5.L, R1.L = R4 [all...] |
H A D | issue175.s | 23 R4 = 0; define 25 R4 = R1 +|+ R0, R0 = R1 -|- R0 (S , ASL); define 26 _DBG R4;
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H A D | issue89.s | 23 R4 = A0.w; define 25 DBGA ( R4.H , 0x003e ); 26 DBGA ( R4.L , 0x0001 );
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H A D | c_alu2op_shadd_1.s | 21 R4 = ( R4 + R0 ) << 1; define 46 R4 = ( R4 + R1 ) << 1; define 71 R4 = ( R4 + R2 ) << 1; define 96 R4 = ( R4 + R3 ) << 1; define 118 R0 = ( R0 + R4 ) << 1; 119 R1 = ( R1 + R4 ) << 125 R4 = ( R4 + R4 ) << 1; define 147 R4 = ( R4 + R5 ) << 1; define 172 R4 = ( R4 + R6 ) << 1; define 197 R4 = ( R4 + R7 ) << 1; define [all...] |
H A D | c_alu2op_shadd_2.s | 21 R4 = ( R4 + R0 ) << 2; define 46 R4 = ( R4 + R1 ) << 2; define 71 R4 = ( R4 + R2 ) << 2; define 96 R4 = ( R4 + R3 ) << 2; define 118 R0 = ( R0 + R4 ) << 2; 119 R1 = ( R1 + R4 ) << 125 R4 = ( R4 + R4 ) << 2; define 147 R4 = ( R4 + R5 ) << 2; define 172 R4 = ( R4 + R6 ) << 2; define 197 R4 = ( R4 + R7 ) << 2; define [all...] |
H A D | c_dsp32shift_align16.s | 19 R4 = ALIGN16 ( R4 , R0 ); define 44 R4 = ALIGN16 ( R4 , R1 ); define 70 R4 = ALIGN16 ( R4 , R2 ); define 95 R4 = ALIGN16 ( R4 , R3 ); define 117 R0 = ALIGN16 ( R0 , R4 ); 118 R1 = ALIGN16 ( R1 , R4 ); 124 R4 = ALIGN16 ( R4 , R4 ); define 146 R4 = ALIGN16 ( R4 , R5 ); define 171 R4 = ALIGN16 ( R4 , R6 ); define 195 R4 = ALIGN16 ( R3 , R7 ); define [all...] |
H A D | c_dsp32shift_align24.s | 19 R4 = ALIGN24 ( R4 , R0 ); define 44 R4 = ALIGN24 ( R4 , R1 ); define 70 R4 = ALIGN24 ( R4 , R2 ); define 95 R4 = ALIGN24 ( R4 , R3 ); define 117 R0 = ALIGN24 ( R0 , R4 ); 118 R1 = ALIGN24 ( R1 , R4 ); 124 R4 = ALIGN24 ( R4 , R4 ); define 146 R4 = ALIGN24 ( R4 , R5 ); define 171 R4 = ALIGN24 ( R4 , R6 ); define 195 R4 = ALIGN24 ( R3 , R7 ); define [all...] |
H A D | c_dsp32shift_align8.s | 19 R4 = ALIGN8 ( R4 , R0 ); define 44 R4 = ALIGN8 ( R4 , R1 ); define 70 R4 = ALIGN8 ( R4 , R2 ); define 95 R4 = ALIGN8 ( R4 , R3 ); define 117 R0 = ALIGN8 ( R0 , R4 ); 118 R1 = ALIGN8 ( R1 , R4 ); 124 R4 = ALIGN8 ( R4 , R4 ); define 146 R4 = ALIGN8 ( R4 , R5 ); define 171 R4 = ALIGN8 ( R4 , R6 ); define 195 R4 = ALIGN8 ( R3 , R7 ); define [all...] |
H A D | c_dsp32shift_fdepx.s | 19 R4 = DEPOSIT( R4, R0 ) (X); define 44 R4 = DEPOSIT( R4, R1 ); define 70 R4 = DEPOSIT( R4, R2 ); define 95 R4 = DEPOSIT( R4, R3 ); define 117 R0 = DEPOSIT( R0, R4 ); 118 R1 = DEPOSIT( R1, R4 ); 124 R4 = DEPOSIT( R4, R4 ); define 149 R4 = DEPOSIT( R5, R5 ); define 171 R4 = DEPOSIT( R4, R6 ); define 195 R4 = DEPOSIT( R3, R7 ); define [all...] |
H A D | c_dsp32shift_lhh.s | 24 R4 = LSHIFT R3 BY R0.L (V); define 25 R5 = LSHIFT R4 BY R0.L (V); 41 R4 = LSHIFT R2 BY R1.L (V); define 43 R6 = LSHIFT R4 BY R1.L (V); 58 R4 = LSHIFT R1 BY R2.L (V); define 61 R7 = LSHIFT R4 BY R2.L (V); 75 R4 = LSHIFT R0 BY R3.L (V); define 79 R0 = LSHIFT R4 BY R3.L (V); 92 R4.L = -1; 93 R0 = LSHIFT R0 BY R4 97 R4 = LSHIFT R4 BY R4.L (V); define 117 R4 = LSHIFT R6 BY R5.L (V); define 134 R4 = LSHIFT R5 BY R6.L (V); define 151 R4 = LSHIFT R4 BY R7.L (V); define 169 R4 = LSHIFT R4 BY R0.L (V); define 187 R4 = LSHIFT R4 BY R1.L (V); define 206 R4 = LSHIFT R4 BY R2.L (V); define 224 R4 = LSHIFT R4 BY R3.L (V); define 260 R4 = LSHIFT R4 BY R5.L (V); define 279 R4 = LSHIFT R4 BY R6.L (V); define 297 R4 = LSHIFT R4 BY R7.L (V); define [all...] |
H A D | c_compi2opd_dr_eq_i7_p.s | 15 R4 = 4; define 32 R4 = 12; define 49 R4 = 20; define 66 R4 = 28; define 83 R4 = 36; define 100 R4 = 44; define 117 R4 = 52; define 134 R4 = 60; define
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/netbsd-current/external/gpl3/gdb.old/dist/sim/testsuite/sim/bfin/ |
H A D | c_alu2op_shadd_1.s | 21 R4 = ( R4 + R0 ) << 1; define 46 R4 = ( R4 + R1 ) << 1; define 71 R4 = ( R4 + R2 ) << 1; define 96 R4 = ( R4 + R3 ) << 1; define 118 R0 = ( R0 + R4 ) << 1; 119 R1 = ( R1 + R4 ) << 125 R4 = ( R4 + R4 ) << 1; define 147 R4 = ( R4 + R5 ) << 1; define 172 R4 = ( R4 + R6 ) << 1; define 197 R4 = ( R4 + R7 ) << 1; define [all...] |
H A D | c_alu2op_shadd_2.s | 21 R4 = ( R4 + R0 ) << 2; define 46 R4 = ( R4 + R1 ) << 2; define 71 R4 = ( R4 + R2 ) << 2; define 96 R4 = ( R4 + R3 ) << 2; define 118 R0 = ( R0 + R4 ) << 2; 119 R1 = ( R1 + R4 ) << 125 R4 = ( R4 + R4 ) << 2; define 147 R4 = ( R4 + R5 ) << 2; define 172 R4 = ( R4 + R6 ) << 2; define 197 R4 = ( R4 + R7 ) << 2; define [all...] |
H A D | c_dsp32shift_align16.s | 19 R4 = ALIGN16 ( R4 , R0 ); define 44 R4 = ALIGN16 ( R4 , R1 ); define 70 R4 = ALIGN16 ( R4 , R2 ); define 95 R4 = ALIGN16 ( R4 , R3 ); define 117 R0 = ALIGN16 ( R0 , R4 ); 118 R1 = ALIGN16 ( R1 , R4 ); 124 R4 = ALIGN16 ( R4 , R4 ); define 146 R4 = ALIGN16 ( R4 , R5 ); define 171 R4 = ALIGN16 ( R4 , R6 ); define 195 R4 = ALIGN16 ( R3 , R7 ); define [all...] |
H A D | c_dsp32shift_align24.s | 19 R4 = ALIGN24 ( R4 , R0 ); define 44 R4 = ALIGN24 ( R4 , R1 ); define 70 R4 = ALIGN24 ( R4 , R2 ); define 95 R4 = ALIGN24 ( R4 , R3 ); define 117 R0 = ALIGN24 ( R0 , R4 ); 118 R1 = ALIGN24 ( R1 , R4 ); 124 R4 = ALIGN24 ( R4 , R4 ); define 146 R4 = ALIGN24 ( R4 , R5 ); define 171 R4 = ALIGN24 ( R4 , R6 ); define 195 R4 = ALIGN24 ( R3 , R7 ); define [all...] |
H A D | c_dsp32shift_align8.s | 19 R4 = ALIGN8 ( R4 , R0 ); define 44 R4 = ALIGN8 ( R4 , R1 ); define 70 R4 = ALIGN8 ( R4 , R2 ); define 95 R4 = ALIGN8 ( R4 , R3 ); define 117 R0 = ALIGN8 ( R0 , R4 ); 118 R1 = ALIGN8 ( R1 , R4 ); 124 R4 = ALIGN8 ( R4 , R4 ); define 146 R4 = ALIGN8 ( R4 , R5 ); define 171 R4 = ALIGN8 ( R4 , R6 ); define 195 R4 = ALIGN8 ( R3 , R7 ); define [all...] |
H A D | c_dsp32shift_fdepx.s | 19 R4 = DEPOSIT( R4, R0 ) (X); define 44 R4 = DEPOSIT( R4, R1 ); define 70 R4 = DEPOSIT( R4, R2 ); define 95 R4 = DEPOSIT( R4, R3 ); define 117 R0 = DEPOSIT( R0, R4 ); 118 R1 = DEPOSIT( R1, R4 ); 124 R4 = DEPOSIT( R4, R4 ); define 149 R4 = DEPOSIT( R5, R5 ); define 171 R4 = DEPOSIT( R4, R6 ); define 195 R4 = DEPOSIT( R3, R7 ); define [all...] |
H A D | c_dsp32shift_lhh.s | 24 R4 = LSHIFT R3 BY R0.L (V); define 25 R5 = LSHIFT R4 BY R0.L (V); 41 R4 = LSHIFT R2 BY R1.L (V); define 43 R6 = LSHIFT R4 BY R1.L (V); 58 R4 = LSHIFT R1 BY R2.L (V); define 61 R7 = LSHIFT R4 BY R2.L (V); 75 R4 = LSHIFT R0 BY R3.L (V); define 79 R0 = LSHIFT R4 BY R3.L (V); 92 R4.L = -1; 93 R0 = LSHIFT R0 BY R4 97 R4 = LSHIFT R4 BY R4.L (V); define 117 R4 = LSHIFT R6 BY R5.L (V); define 134 R4 = LSHIFT R5 BY R6.L (V); define 151 R4 = LSHIFT R4 BY R7.L (V); define 169 R4 = LSHIFT R4 BY R0.L (V); define 187 R4 = LSHIFT R4 BY R1.L (V); define 206 R4 = LSHIFT R4 BY R2.L (V); define 224 R4 = LSHIFT R4 BY R3.L (V); define 260 R4 = LSHIFT R4 BY R5.L (V); define 279 R4 = LSHIFT R4 BY R6.L (V); define 297 R4 = LSHIFT R4 BY R7.L (V); define [all...] |
H A D | c_compi2opd_dr_eq_i7_p.s | 15 R4 = 4; define 32 R4 = 12; define 49 R4 = 20; define 66 R4 = 28; define 83 R4 = 36; define 100 R4 = 44; define 117 R4 = 52; define 134 R4 = 60; define
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H A D | hwloop-branch-in.s | 16 imm32 R4, \exp5; 17 CC = R4 == R5; 19 imm32 R4, \exp6; 20 CC = R4 == R6; 22 imm32 R4, \exp7; 23 CC = R4 == R7; 26 imm32 R4, \expLC; 27 CC = R4 == R3;
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