Searched refs:NewOpc (Results 26 - 50 of 62) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp894 unsigned NewOpc; local
899 NewOpc = AArch64::STPXpre;
902 NewOpc = AArch64::STPDpre;
905 NewOpc = AArch64::STPQpre;
908 NewOpc = AArch64::STRXpre;
911 NewOpc = AArch64::STRDpre;
914 NewOpc = AArch64::STRQpre;
917 NewOpc = AArch64::LDPXpost;
920 NewOpc = AArch64::LDPDpost;
923 NewOpc
[all...]
H A DAArch64ISelLowering.cpp1552 unsigned NewOpc) {
1638 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
1666 unsigned NewOpc; local
1671 NewOpc = Size == 32 ? AArch64::ANDWri : AArch64::ANDXri;
1674 NewOpc = Size == 32 ? AArch64::ORRWri : AArch64::ORRXri;
1677 NewOpc = Size == 32 ? AArch64::EORWri : AArch64::EORXri;
1684 return optimizeLogicalImm(Op, Size, Imm, DemandedBits, TLO, NewOpc);
3682 unsigned NewOpc = 0; local
3687 NewOpc = AArch64ISD::SMULL;
3692 NewOpc
1549 optimizeLogicalImm(SDValue Op, unsigned Size, uint64_t Imm, const APInt &Demanded, TargetLowering::TargetLoweringOpt &TLO, unsigned NewOpc) argument
14642 unsigned NewOpc = getGatherVecOpcode(Scaled, OffsetIsSExt, true); local
14849 unsigned NewOpc = 0; local
15370 unsigned NewOpc = N->getOpcode(); local
15874 unsigned NewOpc; local
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H A DAArch64LoadStoreOptimizer.cpp1784 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1791 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1800 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
H A DAArch64InstrInfo.cpp1450 unsigned NewOpc = convertToNonFlagSettingOpc(CmpInstr); local
1451 if (NewOpc == Opc)
1453 const MCInstrDesc &MCID = get(NewOpc);
1730 unsigned NewOpc = sForm(*MI); local
1731 if (NewOpc == AArch64::INSTRUCTION_LIST_END)
1738 MI->setDesc(get(NewOpc));
4586 unsigned NewOpc = convertToNonFlagSettingOpc(Root);
4589 if (NewOpc == Opc)
4591 Opc = NewOpc;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1915 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; local
1916 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
1925 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; local
1926 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
1935 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; local
1937 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
1955 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc))
2186 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; local
2187 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
2228 unsigned NewOpc; local
2505 unsigned NewOpc = ARM::VLDMDIA; local
2536 unsigned NewOpc = ARM::VSTMDIA; local
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H A DARMISelLowering.cpp3958 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) local
3960 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3965 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm) local
3967 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3974 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu) local
3976 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3983 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) local
3985 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3988 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) local
3990 return DAG.getNode(NewOpc, SDLo
8992 unsigned NewOpc = 0; local
11381 unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM local
11405 unsigned NewOpc; local
11674 unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode()); local
14633 unsigned NewOpc = 0; local
14877 unsigned NewOpc = 0; local
14972 unsigned NewOpc = 0; local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp158 unsigned NewOpc = macToMad(Opc); local
159 if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
164 const MCInstrDesc &MadDesc = TII->get(NewOpc);
352 unsigned NewOpc = macToMad(Opc); local
353 if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
356 MI->setDesc(TII->get(NewOpc));
671 unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(UseMI->getOpcode()); local
672 UseMI->setDesc(TII->get(NewOpc));
H A DAMDGPUInstructionSelector.h94 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
H A DAMDGPUInstructionSelector.cpp92 unsigned NewOpc) const {
93 MI.setDesc(TII.get(NewOpc));
2499 unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; local
2521 BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg)
2555 BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedLo)
2569 BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskedHi)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1565 unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri local
1568 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
1634 unsigned NewOpc = ExtOpc == Hexagon::C2_cmpgei ? Hexagon::C2_cmplt local
1636 BuildMI(MBB, At, dl, HII->get(NewOpc))
1804 unsigned NewOpc = ExtOpc == Hexagon::M2_naccii ? Hexagon::A2_sub local
1806 BuildMI(MBB, At, dl, HII->get(NewOpc))
H A DHexagonInstrInfo.cpp1090 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai local
1092 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1106 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai local
1108 BuildMI(MBB, MI, DL, get(NewOpc),
1113 BuildMI(MBB, MI, DL, get(NewOpc),
1128 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai local
1130 BuildMI(MBB, MI, DL, get(NewOpc))
1145 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai local
1147 BuildMI(MBB, MI, DL, get(NewOpc))
1152 BuildMI(MBB, MI, DL, get(NewOpc))
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H A DHexagonBitSimplify.cpp2143 unsigned NewOpc = (W == 8) ? Hexagon::A2_zxtb
2162 if (!validateReg(RS, NewOpc, 1))
2168 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
2170 if (NewOpc == Hexagon::A2_andir)
2172 else if (NewOpc == Hexagon::S2_extractu)
2380 unsigned NewOpc = V.is(0) ? Hexagon::PS_false : Hexagon::PS_true;
2381 BuildMI(B, At, DL, HII.get(NewOpc), NewR);
H A DHexagonISelLowering.cpp2265 unsigned NewOpc; local
2268 NewOpc = HexagonISD::VASL;
2271 NewOpc = HexagonISD::VASR;
2274 NewOpc = HexagonISD::VLSR;
2287 return DAG.getNode(NewOpc, dl, ty(Op), Op0, S);
2290 return DAG.getNode(NewOpc, dl, ty(Op), Op0, Op1.getOperand(0));
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1346 unsigned NewOpc = 0; local
1356 NewOpc = SystemZ::ASI;
1358 NewOpc = SystemZ::AGSI;
1367 NewOpc = SystemZ::ALSI;
1369 NewOpc = SystemZ::ALGSI;
1398 CurDAG->getMachineNode(NewOpc, DL, MVT::i32, MVT::Other, Ops);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp450 // %LoadResult/%StoreSrc = NewOpc %BaseAddr(p0), 16_bit_signed_immediate
497 const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); local
498 if (NewOpc == I.getOpcode())
501 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
H A DMipsBranchExpansion.cpp337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); local
338 const MCInstrDesc &NewDesc = TII->get(NewOpc);
H A DMipsSEInstrInfo.cpp723 unsigned NewOpc) const {
724 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineLICM.cpp1239 unsigned NewOpc = local
1244 if (NewOpc == 0) return nullptr;
1245 const MCInstrDesc &MID = TII->get(NewOpc);
H A DTwoAddressInstructionPass.cpp1206 unsigned NewOpc = local
1211 if (NewOpc != 0) {
1212 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp503 unsigned NewOpc = local
507 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef});
H A DAArch64InstructionSelector.cpp2637 const unsigned NewOpc =
2639 if (NewOpc == I.getOpcode())
2646 I.setDesc(TII.get(NewOpc));
2652 auto NewInst = MIB.buildInstr(NewOpc, {}, {}, I.getFlags());
2727 unsigned NewOpc = I.getOpcode() == TargetOpcode::G_SMULH ? AArch64::SMULHrr
2729 I.setDesc(TII.get(NewOpc));
2759 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize);
2760 if (NewOpc == I.getOpcode())
2763 I.setDesc(TII.get(NewOpc));
3060 const unsigned NewOpc
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp5721 unsigned NewOpc = 0; local
5725 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
5726 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5727 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5728 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5735 MI.setDesc(get(NewOpc));
6054 unsigned NewOpc = 0; local
6057 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
6058 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6059 case X86::TEST32rr: NewOpc
6361 unsigned NewOpc; local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h541 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp9976 unsigned NewOpc; local
9979 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
9980 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
9981 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
9985 TmpInst.setOpcode(NewOpc);
10499 unsigned NewOpc; local
10502 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
10503 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
10504 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
10505 case ARM::t2UXTB: NewOpc
10594 unsigned NewOpc; local
10630 unsigned NewOpc; local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2860 int NewOpc = PPCInstrInfo::getRecordFormOpcode(NonRecOpc);
2865 if (NewOpc != -1 && IsBitwiseNegate) {
2875 SDValue(CurDAG->getMachineNode(NewOpc, dl,
2879 assert((NewOpc != -1 || !IsBitwiseNegate) &&
2882 SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDI8_rec : NewOpc,
2955 unsigned NewOpc;
2958 case ISD::AND: NewOpc = PPC::AND8; break;
2959 case ISD::OR: NewOpc = PPC::OR8; break;
2960 case ISD::XOR: NewOpc
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