/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86SpeculativeLoadHardening.cpp | 1155 .addReg(TargetReg, RegState::Kill) 1174 .addReg(TargetReg, RegState::Kill) 1175 .addReg(AddrReg, RegState::Kill); 1540 .addReg(PredStateReg, RegState::Kill) 1546 .addReg(TmpReg, RegState::Kill); 1565 .addReg(TmpReg, RegState::Kill) 2171 .addReg(ExpectedRetAddrReg, RegState::Kill) 2182 .addReg(ExpectedRetAddrReg, RegState::Kill) 2183 .addReg(ActualRetAddrReg, RegState::Kill); 2193 .addReg(NewStateReg, RegState::Kill) [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRExpandPseudoInsts.cpp | 683 .addReg(SrcReg, RegState::Kill); 688 .addReg(SrcReg, RegState::Kill); 714 .addReg(SrcReg, RegState::Kill); 719 .addReg(SrcReg, RegState::Kill); 1098 .addReg(DstReg, RegState::Kill) 1104 .addReg(DstReg, RegState::Kill) 1132 .addReg(DstReg, RegState::Kill) 1138 .addReg(DstReg, RegState::Kill) 1921 .addReg(DstHiReg, RegState::Kill); 1925 .addReg(DstHiReg, RegState::Kill) [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIFrameLowering.cpp | 306 .addReg(FlatScrInitHi, RegState::Kill); 316 .addReg(FlatScrInitLo, RegState::Kill) 474 .addReg(PreloadedScratchWaveOffsetReg, RegState::Kill); 629 .addReg(PreloadedScratchRsrcReg, RegState::Kill); 645 // We cannot Kill ScratchWaveOffsetReg here because we allow it to be used in 789 .addReg(ScratchExecCopy, RegState::Kill); 918 .addReg(FramePtrReg, RegState::Kill) 1021 .addReg(TmpVGPR, RegState::Kill); 1047 .addReg(TmpVGPR, RegState::Kill); 1092 .addReg(ScratchExecCopy, RegState::Kill); [all...] |
H A D | SIRegisterInfo.cpp | 228 .addReg(SavedExecReg, RegState::Kill); 707 .addReg(OffsetReg, RegState::Kill) 713 .addReg(OffsetReg, RegState::Kill) 1153 // The last implicit use carries the "Kill" flag. 1180 State &= ~RegState::Kill; 1255 .addReg(TmpReg, RegState::Kill); 1353 // SubReg carries the "Kill" flag when SubReg == SB.SuperReg. 1382 // The last implicit use of the SB.SuperReg carries the "Kill" flag. 1716 .addReg(TmpSReg, RegState::Kill); 1763 MIB.addReg(ScaledReg, RegState::Kill); [all...] |
H A D | SILoadStoreOptimizer.cpp | 1092 BaseRegFlags = RegState::Kill; 1119 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1186 BaseRegFlags = RegState::Kill; 1259 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1309 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1370 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1436 .addReg(DestReg, RegState::Kill, SubRegIdx1); 1471 .addReg(SrcReg, RegState::Kill); 1626 .addReg(SrcReg, RegState::Kill); 1714 .addReg(CarryReg, RegState::Kill) [all...] |
H A D | R600InstrInfo.cpp | 754 .addReg(R600::PREDICATE_BIT, RegState::Kill); 769 .addReg(R600::PREDICATE_BIT, RegState::Kill); 1118 RegState::Implicit | RegState::Kill); 1151 RegState::Implicit | RegState::Kill);
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H A D | SILowerControlFlow.cpp | 253 .addReg(Tmp, RegState::Kill); 691 .addReg(CountReg, RegState::Kill)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 797 MIB.addReg(MustSaveCRs[0], RegState::Kill); 933 .addReg(ScratchReg, RegState::Kill) 940 .addReg(TempReg, RegState::Kill) 943 .addReg(ScratchReg, RegState::Kill) 944 .addReg(TempReg, RegState::Kill); 948 .addReg(SPReg, RegState::Kill) 963 .addReg(ScratchReg, RegState::Kill) 966 .addReg(SPReg, RegState::Kill) 997 .addReg(ScratchReg, RegState::Kill) 1013 .addReg(FPReg, RegState::Kill) // Sav [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
H A D | ARCFrameLowering.cpp | 166 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill); 296 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill); 463 .addReg(Reg, RegState::Kill)
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H A D | ARCRegisterInfo.cpp | 80 KillState = RegState::Kill;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 378 .addReg(Reg, RegState::Kill) 383 .addReg(Reg, RegState::Kill) 393 .addReg(Reg, RegState::Kill) 398 .addReg(Reg, RegState::Kill) 408 .addReg(Reg, RegState::Kill) 639 .addReg(ARM::R12, RegState::Kill) 646 .addReg(ARM::SP, RegState::Kill) 647 .addReg(ARM::R4, RegState::Kill) 824 .addReg(ARM::SP, RegState::Kill) 829 .addReg(ARM::R4, RegState::Kill) [all...] |
H A D | Thumb2InstrInfo.cpp | 284 .addReg(BaseReg, RegState::Kill) 317 .addReg(DestReg, RegState::Kill) 329 .addReg(DestReg, RegState::Kill) 394 .addReg(BaseReg, RegState::Kill)
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H A D | ARMExpandPseudoInsts.cpp | 1155 .addReg(ARM::CPSR, RegState::Kill); 1617 .addReg(DesiredReg, RegState::Kill); 1644 .addReg(ARM::CPSR, RegState::Kill); 1661 .addReg(TempReg, RegState::Kill) 1667 .addReg(ARM::CPSR, RegState::Kill); 1759 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); 1765 .addReg(ARM::CPSR, RegState::Kill); 1781 .addReg(TempReg, RegState::Kill) 1787 .addReg(ARM::CPSR, RegState::Kill); 1846 PushMIB2.addReg(Reg, RegState::Kill); [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 276 MCPhysReg AssignedReg, bool Kill, bool LiveOut); 405 MCPhysReg AssignedReg, bool Kill, bool LiveOut) { 412 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI); 544 /// not used by a virtreg. Kill the physreg, marking it free. This may add 863 .addReg(LRI->PhysReg, llvm::RegState::Kill); 913 bool Kill = LRI->LastUse == nullptr; local 914 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); 404 spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill, bool LiveOut) argument
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H A D | LiveInterval.cpp | 565 SlotIndex StartIdx, SlotIndex Kill) { 568 return CalcLiveRangeUtilSet(this).extendInBlock(Undefs, StartIdx, Kill); 570 return CalcLiveRangeUtilVector(this).extendInBlock(Undefs, StartIdx, Kill); 573 VNInfo *LiveRange::extendInBlock(SlotIndex StartIdx, SlotIndex Kill) { 576 return CalcLiveRangeUtilSet(this).extendInBlock(StartIdx, Kill); 578 return CalcLiveRangeUtilVector(this).extendInBlock(StartIdx, Kill);
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H A D | LiveIntervals.cpp | 642 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill, argument 644 LiveQueryResult LRQ = LR.Query(Kill); 649 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill); 654 LR.removeSegment(Kill, LRQ.endPoint()); 660 LR.removeSegment(Kill, MBBEnd); 1112 // Kill flags shouldn't be used while live intervals exist, they will be 1413 // Kill/dead flags shouldn't be used while live intervals exist; they
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyInstrInfo.cpp | 87 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSERegisterInfo.cpp | 248 .addReg(Reg, RegState::Kill);
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H A D | MipsSEFrameLowering.cpp | 179 .addReg(VR, RegState::Kill); 216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); 218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); 274 .addReg(VR0, RegState::Kill); 277 .addReg(VR1, RegState::Kill);
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H A D | MipsSEInstrInfo.cpp | 611 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 650 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 778 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | LiveIntervals.h | 191 /// If \p LR has a live value at \p Kill, prune its live range by removing 192 /// any liveness reachable from Kill. Add live range end points to 198 void pruneValue(LiveRange &LR, SlotIndex Kill,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kExpandPseudo.cpp | 234 .addReg(JumpTarget.getReg(), RegState::Kill);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 457 .addReg(SrcReg, RegState::Kill) 1378 .addReg(VL, RegState::Kill) 1390 .addReg(VL, RegState::Kill) 1391 .addReg(N, RegState::Kill);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonStoreWidening.cpp | 460 .addReg(VReg, RegState::Kill);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 516 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D) 711 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
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