Searched refs:BI (Results 176 - 200 of 351) sorted by relevance

1234567891011>>

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DLint.cpp235 for (auto BI = I.arg_begin(); BI != AE; ++BI, ++ArgNo) {
243 if (AI != BI && (*BI)->getType()->isPointerTy()) {
244 AliasResult Result = AA->alias(*AI, *BI);
H A DVectorUtils.cpp1052 for (auto BI = AccessStrideInfo.rbegin(), E = AccessStrideInfo.rend();
1053 BI != E; ++BI) {
1054 Instruction *B = BI->first;
1055 StrideDescriptor DesB = BI->second;
1075 for (auto AI = std::next(BI); AI != E; ++AI) {
1098 if (!canReorderMemAccessesForInterleavedGroups(&*AI, &*BI)) {
H A DInlineCost.cpp403 bool visitBranchInst(BranchInst &BI);
750 if (BranchInst *BI = dyn_cast<BranchInst>(&I)) {
752 if (BI->isConditional() &&
754 SimplifiedValues.lookup(BI->getCondition()))) {
1902 bool CallAnalyzer::visitBranchInst(BranchInst &BI) { argument
1907 return BI.isUnconditional() || isa<ConstantInt>(BI.getCondition()) ||
1909 SimplifiedValues.lookup(BI.getCondition()));
2353 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
2354 if (BI
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DStackColoring.cpp574 LivenessMap::const_iterator BI = BlockLiveness.find(MBB); local
575 assert(BI != BlockLiveness.end() && "Block not found");
576 const BlockLifetimeInfo &BlockInfo = BI->second;
815 LivenessMap::iterator BI = BlockLiveness.find(BB); local
816 assert(BI != BlockLiveness.end() && "Block not found");
817 BlockLifetimeInfo &BlockInfo = BI->second;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DGVNSink.cpp275 auto BI = Blocks.begin(); local
277 while (BI != Blocks.end()) {
279 if (!llvm::is_contained(NewBlocks, *BI)) {
280 BI = Blocks.erase(BI);
283 ++BI;
H A DReassociate.cpp810 /// Insert instructions before the instruction pointed to by BI,
812 /// version of the value is returned, and BI is left pointing at the instruction
817 static Value *NegateValue(Value *V, Instruction *BI, argument
835 I->setOperand(0, NegateValue(I->getOperand(0), BI, ToRedo));
836 I->setOperand(1, NegateValue(I->getOperand(1), BI, ToRedo));
847 I->moveBefore(BI);
869 if (TheNeg->getParent()->getParent() != BI->getParent()->getParent())
900 // create the neg before BI, as if we hadn't found an existing
910 TheNeg->andIRFlags(BI);
918 Instruction *NewNeg = CreateNeg(V, V->getName() + ".neg", BI, B
[all...]
H A DSCCP.cpp548 for (BasicBlock::iterator BI = BB.begin(), E = BB.end(); BI != E;) {
549 Instruction *Inst = &*BI++;
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSearchableTableEmitter.cpp120 } else if (BitsInit *BI = dyn_cast<BitsInit>(I))
121 return "0x" + utohexstr(getAsInt(BI));
122 else if (BitInit *BI = dyn_cast<BitInit>(I))
123 return BI->getValue() ? "true" : "false";
164 } else if (BitsRecTy *BI = dyn_cast<BitsRecTy>(Field.RecType)) {
165 unsigned NumBits = BI->getNumBits();
H A DFixedLenDecoderEmitter.cpp1902 VarBitInit *BI = dyn_cast<VarBitInit>(Bits.getBit(bi));
1903 if (BI)
1904 Var = dyn_cast<VarInit>(BI->getBitVar());
1924 VarBitInit *BI = dyn_cast<VarBitInit>(Bits.getBit(bi));
1925 if (BI)
1926 Var = dyn_cast<VarInit>(BI->getBitVar());
2077 VarBitInit *BI = dyn_cast<VarBitInit>(Bits.getBit(bi));
2078 if (BI)
2079 Var = dyn_cast<VarInit>(BI->getBitVar());
2107 Offset = BI
[all...]
H A DCodeGenTarget.cpp525 BitsInit *BI = R->getValueAsBitsInit("Inst"); local
527 unsigned numBits = BI->getNumBits();
533 Init *OrigBit = BI->getBit(bit);
534 Init *BitSwap = BI->getBit(bitSwapIdx);
540 NewBits[middle] = BI->getBit(middle);
/netbsd-current/external/gpl3/gdb.old/dist/sim/frv/
H A Dfrv-sim.h75 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
739 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
848 BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
851 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
852 void frvbf_commit (SIM_CPU *, SI, BI);
/netbsd-current/external/gpl3/gdb/dist/sim/frv/
H A Dfrv-sim.h75 extern void frvbf_h_psr_s_set_handler (SIM_CPU *, BI);
746 USI frv_rett (SIM_CPU *current_cpu, PCADDR pc, BI debug_field);
855 BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
860 void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
861 void frvbf_commit (SIM_CPU *, SI, BI);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp749 if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
751 if (!BI->isConditional() ||
752 !BI->extractProfMetadata(TrueWeight, FalseWeight))
757 bool TrueIsExit = !L->contains(BI->getSuccessor(0));
1245 bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
1250 if (canSaveCmp(*I, BI, SE, LI, DT, AC, LibInfo))
1264 *BI = HWLoopInfo.ExitBranch;
H A DPPCMIPeephole.cpp1023 static bool isEqOrNe(MachineInstr *BI) { argument
1024 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
1056 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) { argument
1062 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
1075 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) { argument
1081 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
1203 MachineInstr *BI = &*MBB.getFirstInstrTerminator();
1204 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg());
/netbsd-current/sys/arch/powerpc/powerpc/
H A Ddb_disasm.c629 u_int BO, BI; local
631 BI = extract_field(instr, 31 - 15, 5);
643 condstr[((BO & 8) >> 1) + (BI & 3)]);
644 if (BI >= 4)
778 u_int BI; local
779 BI = extract_field(instr, 31 - 15, 5);
780 db_printf("%d, ", BI);
/netbsd-current/external/apache2/llvm/dist/clang/lib/Analysis/
H A DThreadSafety.cpp781 for (const auto &BI : *CurrBlock) {
782 switch (BI.getKind()) {
784 CFGStmt CS = BI.castAs<CFGStmt>();
826 for (CFGBlock::const_reverse_iterator BI = CurrBlock->rbegin(),
827 BE = CurrBlock->rend(); BI != BE; ++BI) {
829 if (Optional<CFGStmt> CS = BI->getAs<CFGStmt>()) {
839 for (const auto &BI : *CurrBlock) {
841 if (Optional<CFGStmt> CS = BI.getAs<CFGStmt>()) {
2478 for (const auto &BI
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/IR/
H A DMetadata.cpp1030 int BI = 0;
1033 while (AI < AN && BI < BN) {
1035 ConstantInt *BLow = mdconst::extract<ConstantInt>(B->getOperand(2 * BI));
1043 mdconst::extract<ConstantInt>(B->getOperand(2 * BI + 1)));
1044 ++BI;
1052 while (BI < BN) {
1053 addRange(EndPoints, mdconst::extract<ConstantInt>(B->getOperand(2 * BI)),
1054 mdconst::extract<ConstantInt>(B->getOperand(2 * BI + 1)));
1055 ++BI;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DSCCPSolver.cpp559 if (auto *BI = dyn_cast<BranchInst>(&TI)) {
560 if (BI->isUnconditional()) {
565 ValueLatticeElement BCValue = getValueState(BI->getCondition());
1482 if (auto *BI = dyn_cast<BranchInst>(TI)) {
1483 if (!BI->isConditional())
1485 if (!getValueState(BI->getCondition()).isUnknownOrUndef())
1490 if (isa<UndefValue>(BI->getCondition())) {
1491 BI->setCondition(ConstantInt::getFalse(BI->getContext()));
H A DLoopUnrollAndJam.cpp306 BranchInst *BI = dyn_cast<BranchInst>(LatchBlock->getTerminator()); local
307 assert(BI && !BI->isUnconditional());
308 bool ContinueOnTrue = L->contains(BI->getSuccessor(0));
309 BasicBlock *LoopExit = BI->getSuccessor(ContinueOnTrue);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp827 for (MachineFunction::iterator BI = MF.begin();
828 BI != MF.end(); BI = NextBB) {
829 NextBB = std::next(BI);
830 MachineBasicBlock *MBB = &*BI;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp1268 auto *BI = dyn_cast<BranchInst>(IDom->getTerminator()); local
1269 if (!BI || BI->isUnconditional())
1274 BasicBlockEdge TrueOutEdge(IDom, BI->getSuccessor(0));
1275 BasicBlockEdge FalseOutEdge(IDom, BI->getSuccessor(1));
1280 auto *Cond = BI->getCondition();
/netbsd-current/external/gpl3/gcc/dist/contrib/vim-gcc-dev/syntax/
H A Dgcc-rtl.vim50 syn keyword rtlModes VOID BLK BI QI HI SI DI TI SF DF CC QQ HQ SQ
/netbsd-current/external/gpl3/gcc.old/dist/contrib/vim-gcc-dev/syntax/
H A Dgcc-rtl.vim50 syn keyword rtlModes VOID BLK BI QI HI SI DI TI SF DF CC QQ HQ SQ
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp388 for (auto BI : CurrentPacketMIs) {
389 LLVM_DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
390 if (HII->isDotCurInst(*BI)) {
391 MI = BI;
395 for (auto &MO : BI->operands())
445 for (auto BI : CurrentPacketMIs) {
446 LLVM_DEBUG(dbgs() << "packet has "; BI->dump(););
447 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
H A DBitTracker.h64 void visitBranchesFrom(const MachineInstr &BI);
477 virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,

Completed in 267 milliseconds

1234567891011>>