Searched refs:ADDC (Results 51 - 69 of 69) sorted by relevance
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.cpp | 214 if (Opc == ISD::ADDC) {
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H A D | MipsSEISelLowering.cpp | 109 setOperationAction(ISD::ADDC, MVT::i32, Legal);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 762 unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c 897 case HexagonISD::ADDC:
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H A D | HexagonISelLowering.cpp | 1865 case HexagonISD::ADDC: return "HexagonISD::ADDC"; 3077 return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 2157 case ISD::ADDC: 2580 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 2582 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 2587 ISD::ADDC : ISD::SUBC, 2593 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps); 2689 if (N->getOpcode() == ISD::ADDC) { 2690 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
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H A D | DAGCombiner.cpp | 1615 case ISD::ADDC: return visitADDC(N); 2729 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0); 2871 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); 5115 APInt ADDC = ADDI->getAPIntValue(); local 5117 if (ADDC.getMinSignedBits() <= 64 && 5119 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 5123 ADDC |= Mask; 5124 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 5128 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
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H A D | SelectionDAG.cpp | 3355 case ISD::ADDC: 3943 case ISD::ADDC:
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H A D | TargetLowering.cpp | 6394 bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) && 6397 Next = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), Next,
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 69 setOperationAction(ISD::ADDC, VT, Legal);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 788 // ADDC/ADDE/SUBC/SUBE default to expand. 789 setOperationAction(ISD::ADDC, VT, Expand);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1652 MAKE_CASE(ARMISD::ADDC) 4700 // We use ADDC here to correspond to its use in LowerUnsignedALUO. 4702 Value = DAG.getNode(ARMISD::ADDC, dl, 4810 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS); 12171 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by 12176 // loAdd -> ADDC | 12195 // Check that we are chained to the right ADDC or SUBC node. 12198 AddcSubcNode->getOpcode() != ARMISD::ADDC) || 12212 "Expect ADDC with two result values. First: i32"); 12214 // Check that the ADDC add [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 3850 case PPC::ADDC: 3857 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
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H A D | PPCISelLowering.cpp | 216 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry. 219 setOperationAction(ISD::ADDC, VT, Legal); 16577 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
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/netbsd-current/sys/external/bsd/sljit/dist/sljit_src/ |
H A D | sljitNativePPC_common.c | 139 #define ADDC (HI(31) | LO(10)) macro
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 2436 case ISD::ADDC:
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 232 setOperationAction(ISD::ADDC, VT, Expand);
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H A D | AMDGPUISelLowering.cpp | 377 // AMDGPU uses ADDC/SUBC/ADDE/SUBE 378 setOperationAction(ISD::ADDC, VT, Legal);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 130 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 501 setOperationAction(ISD::ADDC, MVT::i32, Custom); 505 setOperationAction(ISD::ADDC, MVT::i64, Custom); 3128 case ISD::ADDC: 4497 case ISD::ADDC:
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