/netbsd-6-1-5-RELEASE/sys/dev/pci/ |
H A D | if_vge.c | 259 #define CSR_WRITE_4(sc, reg, val) \ macro 278 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 285 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 703 CSR_WRITE_4(sc, VGE_MAR0, 0); 704 CSR_WRITE_4(sc, VGE_MAR1, 0); 713 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 714 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 756 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 757 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 1503 CSR_WRITE_4(s [all...] |
H A D | if_vr.c | 279 #define CSR_WRITE_4(sc, reg, val) \ macro 338 CSR_WRITE_4(sc, reg, \ 342 CSR_WRITE_4(sc, reg, \ 473 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 474 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 479 CSR_WRITE_4(sc, VR_MAR0, 0); 480 CSR_WRITE_4(sc, VR_MAR1, 0); 506 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 507 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 822 CSR_WRITE_4(s [all...] |
H A D | if_kse.c | 64 #define CSR_WRITE_4(sc, off, val) \ macro 724 CSR_WRITE_4(sc, TDLB, KSE_CDTXADDR(sc, 0)); 725 CSR_WRITE_4(sc, RDLB, KSE_CDRXADDR(sc, 0)); 768 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 769 CSR_WRITE_4(sc, MDRXC, sc->sc_rxc); 770 CSR_WRITE_4(sc, MDRSC, 1); 776 CSR_WRITE_4(sc, INTST, ~0); 777 CSR_WRITE_4(sc, INTEN, sc->sc_inten); 814 CSR_WRITE_4(sc, MDTXC, sc->sc_txc); 815 CSR_WRITE_4(s [all...] |
H A D | if_tireg.h | 39 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 909 CSR_WRITE_4(x, TI_MB_JUMBORXPROD_IDX, y); \ 913 CSR_WRITE_4(x, TI_MB_MINIRXPROD_IDX, y) 919 CSR_WRITE_4(x, TI_MB_STDRXPROD_IDX, y); \ 965 #define CSR_WRITE_4(sc, reg, val) \ macro 971 #define CSR_WRITE_4(sc, reg, val) \ macro 979 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 981 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
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H A D | if_sk.c | 250 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 261 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 272 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 283 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 284 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x); 286 CSR_WRITE_4(sc, reg, x); 294 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 305 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg)); 1991 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START); 2175 CSR_WRITE_4(s [all...] |
H A D | if_msk.c | 206 CSR_WRITE_4(sc, reg, x); 851 CSR_WRITE_4(sc, SK_I2CHWIRQ, 1); 858 CSR_WRITE_4(sc, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP); 1868 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 1942 CSR_WRITE_4(sc, SK_STAT_BMU_CSR, SK_STAT_BMU_IRQ_CLEAR); 1946 CSR_WRITE_4(sc, SK_Y2_ICR, 2); 2223 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask); 2275 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
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H A D | if_etreg.h | 354 #define CSR_WRITE_4(sc, reg, val) \ macro
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H A D | if_agereg.h | 854 #define CSR_WRITE_4(sc, reg, val) \ macro 866 CSR_WRITE_4(_sc, AGE_MBOX, \
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H A D | if_alcreg.h | 1187 #define CSR_WRITE_4(_sc, reg, val) \ macro
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H A D | if_alereg.h | 951 #define CSR_WRITE_4(_sc, reg, val) \ macro
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H A D | if_bgereg.h | 128 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 1932 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
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H A D | if_skreg.h | 1563 #define CSR_WRITE_4(sc, reg, val) \ macro
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/netbsd-6-1-5-RELEASE/sys/dev/ic/ |
H A D | wivar.h | 229 #define CSR_WRITE_4(sc, reg, val) \ macro 251 #define CSR_WRITE_4(sc, reg, val) \ macro
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H A D | i82557.c | 521 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 1139 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1635 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1712 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1749 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1871 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDCONFIGOFF); 1906 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDIASOFF); 1978 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, FXP_CDTXADDR(sc, sc->sc_txlast)); 1987 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 2126 CSR_WRITE_4(s [all...] |
H A D | bwi.c | 756 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 759 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1078 CSR_WRITE_4(sc, BWI_MAC_TMPLT_CTRL, ofs); 1079 CSR_WRITE_4(sc, BWI_MAC_TMPLT_DATA, val); 1126 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); 1140 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); 1144 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, 1150 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); 1169 CSR_WRITE_4(sc, BWI_MOBJ_CTRL, BWI_MOBJ_CTRL_VAL(obj_id, ofs)); 1182 CSR_WRITE_4(s [all...] |
H A D | bwivar.h | 85 #define CSR_WRITE_4(sc, reg, val) \ macro 91 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits)) 96 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits)) 101 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
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H A D | rtl81x9var.h | 273 #define CSR_WRITE_4(sc, reg, val) \ macro
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H A D | i82557var.h | 361 #define CSR_WRITE_4(sc, reg, val) \ macro
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/netbsd-6-1-5-RELEASE/sys/arch/sandpoint/stand/altboot/ |
H A D | vge.c | 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro 293 CSR_WRITE_4(l, VR_RDB, VTOPHYS(rxd)); 296 CSR_WRITE_4(l, VR_TDB0, VTOPHYS(txd)); 307 CSR_WRITE_4(l, VR_ISR, ~0); 308 CSR_WRITE_4(l, VR_IEN, 0);
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H A D | nvt.c | 51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro 228 CSR_WRITE_4(l, VR_RDBA, VTOPHYS(rxd)); 229 CSR_WRITE_4(l, VR_TDBA, VTOPHYS(txd));
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H A D | dsk.c | 58 #define CSR_WRITE_4(r,v) out32rb(r,v) macro
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/netbsd-6-1-5-RELEASE/sys/arch/evbarm/ixm1200/ |
H A D | nappi_nppb.c | 71 #define CSR_WRITE_4(sc, reg, val) \ macro
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