/macosx-10.9.5/llvmCore-3425.0.33/lib/MC/ |
H A D | MCCodeGenInfo.cpp | 19 CodeGenOpt::Level OL) { 22 OptLevel = OL; 18 InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
H A D | SparcTargetMachine.cpp | 32 CodeGenOpt::Level OL, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 84 CodeGenOpt::Level OL) 85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 96 CodeGenOpt::Level OL) 97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 78 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 90 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | SparcTargetMachine.h | 39 CodeGenOpt::Level OL, bool is64bit); 70 CodeGenOpt::Level OL); 82 CodeGenOpt::Level OL);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | MipsTargetMachine.cpp | 42 CodeGenOpt::Level OL, 44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 65 CodeGenOpt::Level OL) 66 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 74 CodeGenOpt::Level OL) 75 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 39 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument 62 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 71 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | MipsTargetMachine.h | 46 CodeGenOpt::Level OL, 91 CodeGenOpt::Level OL); 102 CodeGenOpt::Level OL);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.cpp | 70 CodeGenOpt::Level OL, 72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 87 CodeGenOpt::Level OL) 88 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 97 CodeGenOpt::Level OL) 98 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 63 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions& Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 93 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
H A D | PPCTargetMachine.cpp | 39 CodeGenOpt::Level OL, 41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 59 CodeGenOpt::Level OL) 60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 69 CodeGenOpt::Level OL) 70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 35 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument 55 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 65 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | PPCTargetMachine.h | 44 CodeGenOpt::Level OL, bool is64Bit); 81 CodeGenOpt::Level OL); 92 CodeGenOpt::Level OL);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
H A D | MSP430TargetMachine.cpp | 33 CodeGenOpt::Level OL) 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/ |
H A D | XCoreTargetMachine.cpp | 27 CodeGenOpt::Level OL) 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMTargetMachine.cpp | 44 CodeGenOpt::Level OL) 45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 60 CodeGenOpt::Level OL) 61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 86 CodeGenOpt::Level OL) 87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 40 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 56 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | ARMTargetMachine.h | 46 CodeGenOpt::Level OL); 75 CodeGenOpt::Level OL); 118 CodeGenOpt::Level OL);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ |
H A D | TargetMachineC.cpp | 101 CodeGenOpt::Level OL; local 105 OL = CodeGenOpt::None; 108 OL = CodeGenOpt::Less; 111 OL = CodeGenOpt::Aggressive; 114 OL = CodeGenOpt::Default; 120 CM, OL));
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 37 CodeGenOpt::Level OL) 38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 60 CodeGenOpt::Level OL) 61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 76 CodeGenOpt::Level OL, 78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 56 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 72 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
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H A D | X86TargetMachine.h | 43 CodeGenOpt::Level OL, 92 CodeGenOpt::Level OL); 121 CodeGenOpt::Level OL);
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/ |
H A D | MCCodeGenInfo.h | 38 CodeGenOpt::Level OL = CodeGenOpt::Default);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CppBackend/ |
H A D | CPPTargetMachine.h | 28 CodeGenOpt::Level OL) 25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/MCTargetDesc/ |
H A D | SPUMCTargetDesc.cpp | 67 CodeGenOpt::Level OL) { 71 X->InitMCCodeGenInfo(Reloc::Static, CM, OL); 65 createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUTargetMachine.cpp | 38 CodeGenOpt::Level OL) 39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCTargetDesc.cpp | 68 CodeGenOpt::Level OL) { 72 X->InitMCCodeGenInfo(Reloc::Static, CM, OL); 66 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/ |
H A D | MBlazeTargetMachine.cpp | 38 CodeGenOpt::Level OL) 39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCTargetDesc.cpp | 55 CodeGenOpt::Level OL) { 57 X->InitMCCodeGenInfo(RM, CM, OL); 53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/MCTargetDesc/ |
H A D | NVPTXMCTargetDesc.cpp | 56 CodeGenOpt::Level OL) { 58 X->InitMCCodeGenInfo(RM, CM, OL); 54 createNVPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 55 CodeGenOpt::Level OL) { 57 X->InitMCCodeGenInfo(RM, CM, OL); 53 createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 66 CodeGenOpt::Level OL) { 68 X->InitMCCodeGenInfo(RM, CM, OL); 64 createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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