/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_1_sh_mask.h | 56 #define BUS_CNTL__SET_AZ_TC__SHIFT 0xa 116 #define HW_DEBUG__HW_10_DEBUG__SHIFT 0xa 168 #define SLAVE_REQ_CREDIT_CNTL__BIF_HDP_REQ_CREDIT__SHIFT 0xa 248 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa 272 #define SMBDAT_PAD_CNTL__SMBDAT_PAD_WAKE__SHIFT 0xa 296 #define SMBCLK_PAD_CNTL__SMBCLK_PAD_WAKE__SHIFT 0xa 328 #define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa 418 #define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa 442 #define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa 542 #define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0xa [all...] |
/linux-master/sound/soc/amd/include/ |
H A D | acp_2_2_sh_mask.h | 788 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa 846 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa 974 #define ACP_CONTROL__JtagEn__SHIFT 0xa 1032 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa 1096 #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa 1112 #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa 1148 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa 1166 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa 1214 #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa 1216 #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/athub/ |
H A D | athub_2_0_0_sh_mask.h | 54 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 61 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 93 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 180 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 357 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 785 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 818 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 1071 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 1082 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 1093 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa [all...] |
H A D | athub_2_1_0_sh_mask.h | 62 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 81 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 334 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 486 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 551 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 627 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 660 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 1137 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 1148 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 1159 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gca/ |
H A D | gfx_8_1_enum.h | 73 BLEND_SRC_ALPHA_SATURATE = 0xa, 113 CMASK_CLR10_F2 = 0xa, 136 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, 595 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, 646 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, 668 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, 769 STENCIL_AND = 0xa, 799 DB_PERF_SEL_DB_SC_tile_sends = 0xa, 1095 GRBM_PERF_SEL_RESERVED_6 = 0xa, 1131 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, [all...] |
H A D | gfx_8_0_enum.h | 73 BLEND_SRC_ALPHA_SATURATE = 0xa, 113 CMASK_CLR10_F2 = 0xa, 136 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, 586 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, 637 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, 659 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, 760 STENCIL_AND = 0xa, 790 DB_PERF_SEL_DB_SC_tile_sends = 0xa, 1077 GRBM_PERF_SEL_RESERVED_6 = 0xa, 1113 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, [all...] |
H A D | gfx_7_2_enum.h | 72 BLEND_SRC_ALPHA_SATURATE = 0xa, 112 CMASK_CLR10_F2 = 0xa, 130 CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, 410 CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, 458 CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, 477 CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, 575 STENCIL_AND = 0xa, 605 DB_PERF_SEL_DB_SC_tile_sends = 0xa, 892 GRBM_PERF_SEL_RESERVED_6 = 0xa, 928 GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/nbif/ |
H A D | nbif_6_3_1_sh_mask.h | 39 #define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa 73 #define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa 216 #define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa 289 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 323 #define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa 353 #define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa 391 #define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 432 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa 473 #define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa 519 #define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
H A D | vcn_2_6_0_sh_mask.h | 101 #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 191 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 218 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 276 #define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa 800 #define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 842 #define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 916 #define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 985 #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 1027 #define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 1178 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
H A D | nbio_7_7_0_sh_mask.h | 97 #define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa 261 #define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa 290 #define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa 357 #define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 391 #define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa 460 #define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa 524 #define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 565 #define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa 629 #define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa 708 #define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_8_2_sh_mask.h | 80 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa 110 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa 156 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa 204 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa 358 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa 438 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa 516 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa 556 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa 602 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa 628 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa [all...] |
/linux-master/crypto/ |
H A D | dh.c | 19 MPI xa; /* Value is guaranteed to be set. */ member in struct:dh_ctx 26 mpi_free(ctx->xa); 32 * ya = g^xa mod p; [RFC2631 sec 2.1.1] 34 * ZZ = yb^xa mod p; [RFC2631 sec 2.1.1] 38 /* val = base^xa mod p */ 39 return mpi_powm(val, base, ctx->xa, ctx->p); 86 ctx->xa = mpi_read_raw_data(params.key, params.key_size); 87 if (!ctx->xa) 178 if (unlikely(!ctx->xa)) {
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/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_device.c | 72 xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); 75 xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); 94 xa_for_each(&xef->exec_queue.xa, idx, q) { 99 xa_destroy(&xef->exec_queue.xa); 102 xa_for_each(&xef->vm.xa, idx, vm) 105 xa_destroy(&xef->vm.xa);
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/smuio/ |
H A D | smuio_13_0_3_sh_mask.h | 123 #define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa 227 #define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 303 #define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa
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/linux-master/drivers/ata/pata_parport/ |
H A D | epat.c | 242 /* WR(0xe,0xa);WR(0xf,4); */ 260 WR(0xa, 0x38); 296 WR(0x13, 1); WR(0x13, 0); WR(0xa, 0x11); 321 WR(0xa, 0x38); /* read the version code */
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/linux-master/drivers/platform/x86/intel/pmt/ |
H A D | class.c | 255 ret = xa_alloc(ns->xa, &entry->devid, entry, PMT_XA_LIMIT, GFP_KERNEL); 318 xa_erase(ns->xa, entry->devid); 360 xa_erase(ns->xa, entry->devid);
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/ |
H A D | smu_7_0_0_sh_mask.h | 38 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 50 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 62 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa 74 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa 96 #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa 160 #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0xa 190 #define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT 0xa 218 #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa 280 #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa 476 #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa [all...] |
/linux-master/drivers/scsi/aic7xxx/aicasm/ |
H A D | aicasm_insformat.h | 186 #define AIC_OP_JNC 0xa
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/linux-master/arch/sparc/include/uapi/asm/ |
H A D | traps.h | 44 #define SP_TRAP_TOF 0xa /* Tag Overflow */
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/linux-master/include/sound/ |
H A D | snd_wavefront.h | 73 #define fx_dsp_addr base + 0xa
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/linux-master/sound/soc/atmel/ |
H A D | atmel-classd.h | 90 #define CLASSD_INTPMR_EQCFG_T_BOOST_6 0xa
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/linux-master/sound/pci/au88x0/ |
H A D | au88x0_synth.c | 269 case 0xa: /* ctrl */ 305 vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */ 320 vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */ 367 edx >>= 0xa;
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/linux-master/drivers/misc/ibmasm/ |
H A D | dot_command.c | 77 vpd_command[3] = 0xa;
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/linux-master/drivers/staging/rtl8723bs/hal/ |
H A D | HalBtc8723b2Ant.h | 47 BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
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/linux-master/drivers/tee/optee/ |
H A D | optee_msg.h | 35 #define OPTEE_MSG_ATTR_TYPE_TMEM_OUTPUT 0xa
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