/linux-master/sound/soc/fsl/ |
H A D | fsl_spdif.h | 63 #define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET) 67 #define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET) 75 #define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET) 79 #define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET) 84 #define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET) 103 #define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET) 106 #define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
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/linux-master/drivers/gpu/drm/xlnx/ |
H A D | zynqmp_disp_regs.h | 29 #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 98 #define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX 0x3 122 #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0) 128 #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2) 134 #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4) 166 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3 171 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY (0x3 << 4)
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/linux-master/sound/soc/codecs/ |
H A D | nau8822.h | 87 #define NAU8822_REFIMP_MASK 0x3 90 #define NAU8822_REFIMP_3K 0x3 98 #define NAU8822_AIFMT_MASK (0x3 << 3) 99 #define NAU8822_WLEN_MASK (0x3 << 5) 102 #define NAU8822_WLEN_32 (0x3 << 5) 122 #define NAU8822_BCLKDIV_8 (0x3 << 2) 134 #define NAU8822_SMPLR_16K (0x3 << 1)
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H A D | rt1011.h | 304 #define RT1011_FS_SYS_PRE_MASK (0x3 << 14) 309 #define RT1011_FS_SYS_PRE_RCCLK (0x3 << 14) 318 #define RT1011_PLL2_SRC_DIV_MASK (0x3 << 10) 320 #define RT1011_SRCIN_DIV_MASK (0x3 << 8) 370 #define RT1011_I2S_TX_DL_32B (0x3 << 8) 377 #define RT1011_I2S_RX_DL_32B (0x3 << 5) 390 #define RT1011_I2S_TDM_DF_PCM_B (0x3) 400 #define RT1011_TCON_DF_PCM_B (0x3 << 13) 403 #define RT1011_TCON_BCLK_SEL_MASK (0x3 << 10) 408 #define RT1011_TCON_BCLK_SEL_256FS (0x3 << 1 [all...] |
H A D | rt5670.h | 223 #define RT5670_ID_MASK (0x3 << 1) 309 #define RT5670_STO1_ADC_L_BST_MASK (0x3 << 14) 311 #define RT5670_STO1_ADC_R_BST_MASK (0x3 << 12) 313 #define RT5670_STO1_ADC_COMP_MASK (0x3 << 10) 315 #define RT5670_STO2_ADC_L_BST_MASK (0x3 << 8) 317 #define RT5670_STO2_ADC_R_BST_MASK (0x3 << 6) 319 #define RT5670_STO2_ADC_COMP_MASK (0x3 << 4) 339 #define RT5670_DMIC_SRC_MASK (0x3 << 8) 361 #define RT5670_MONO_DMIC_L_SRC_MASK (0x3 << 8) 373 #define RT5670_MONO_DMIC_R_SRC_MASK (0x3) [all...] |
H A D | rt5660.h | 179 #define RT5660_STO1_ADC_L_BST_MASK (0x3 << 14) 181 #define RT5660_STO1_ADC_R_BST_MASK (0x3 << 12) 223 #define RT5660_IF1_DAC_IN_SEL (0x3 << 14) 225 #define RT5660_IF1_ADC_IN_SEL (0x3 << 12) 275 #define RT5660_G_BST3_SM_MASK (0x3 << 14) 277 #define RT5660_G_BST1_SM_MASK (0x3 << 12) 279 #define RT5660_G_DACl_SM_MASK (0x3 << 10) 281 #define RT5660_G_DACR_SM_MASK (0x3 << 8) 283 #define RT5660_G_OM_L_SM_MASK (0x3 << 6) 443 #define RT5660_I2S_O_CP_MASK (0x3 << 1 [all...] |
/linux-master/arch/x86/crypto/ |
H A D | aria-aesni-avx2-asm_64.S | 69 #define transpose_4x4(x0, x1, x2, x3, t1, t2) \ 73 vpunpckldq x3, x2, t1; \ 74 vpunpckhdq x3, x2, x2; \ 79 vpunpckhqdq x2, t2, x3; \ 187 #define inpack16_pre(x0, x1, x2, x3, \ 195 vmovdqu (3 * 32)(rio), x3; \ 210 #define inpack16_post(x0, x1, x2, x3, \ 215 byteslice_16x16b(x0, x1, x2, x3, \ 224 vmovdqu x3, 3 * 32(mem_ab); \ 238 #define write_output(x0, x1, x2, x3, \ [all...] |
H A D | aria-aesni-avx-asm_64.S | 53 #define transpose_4x4(x0, x1, x2, x3, t1, t2) \ 57 vpunpckldq x3, x2, t1; \ 58 vpunpckhdq x3, x2, x2; \ 63 vpunpckhqdq x2, t2, x3; \ 171 #define inpack16_pre(x0, x1, x2, x3, \ 179 vmovdqu (3 * 16)(rio), x3; \ 194 #define inpack16_post(x0, x1, x2, x3, \ 199 byteslice_16x16b(x0, x1, x2, x3, \ 208 vmovdqu x3, 3 * 16(mem_ab); \ 222 #define write_output(x0, x1, x2, x3, \ [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_11_2_enum.h | 39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3, 81 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3, 136 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3, 175 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3, 193 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3, 211 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3, 237 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3, 259 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3, 285 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3, 311 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_6_0_enum.h | 31 UVDFC_MBLOCK_ADDR = 0x3, 44 DBG_BLOCK_ID_PDMA = 0x3, 301 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 423 DBG_BLOCK_ID_SQ_BY4 = 0x3, 485 DBG_BLOCK_ID_CP0_BY8 = 0x3, 517 DBG_BLOCK_ID_MCD_BY16 = 0x3, 534 ENDIAN_8IN64 = 0x3, 540 ARRAY_1D_TILED_THICK = 0x3, 558 CONFIG_8_PIPE = 0x3, 572 CONFIG_8KB_ROW = 0x3, [all...] |
/linux-master/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_reg.h | 153 #define IN_BPC_12_BITS (0x3 << 4) 157 #define IN_COLOR_F_MASK (0x3 << 0) 199 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 203 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 207 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 211 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 228 #define TX_CUR_16_MA (0x3 << 0) 238 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 242 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 310 #define M_VID_UPDATE_CTRL (0x3 << [all...] |
/linux-master/drivers/media/usb/dvb-usb/ |
H A D | af9005-script.h | 39 {0xa00f, 0x0, 0x3, 0x4}, 40 {0xa00f, 0x3, 0x3, 0x5}, 41 {0xa010, 0x0, 0x3, 0x4}, 42 {0xa010, 0x3, 0x3, 0x5}, 43 {0xa016, 0x4, 0x4, 0x3}, 70 {0xa60e, 0x2, 0x2, 0x3}, 78 {0xa2bc, 0x3, 0x1, 0x0}, 85 {0xa60e, 0x6, 0x2, 0x3}, [all...] |
/linux-master/arch/arm64/boot/dts/freescale/ |
H A D | imx8ulp-pinfunc.h | 177 #define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 190 #define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 203 #define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 205 #define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 227 #define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 239 #define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 252 #define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 264 #define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 275 #define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 278 #define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 [all...] |
/linux-master/scripts/dtc/include-prefixes/arm64/freescale/ |
H A D | imx8ulp-pinfunc.h | 177 #define MX8ULP_PAD_PTD16__LPSPI4_PCS1 0x0040 0x08F8 0x3 0x1 190 #define MX8ULP_PAD_PTD17__LPSPI4_PCS2 0x0044 0x08FC 0x3 0x1 203 #define MX8ULP_PAD_PTD18__LPSPI4_PCS3 0x0048 0x0900 0x3 0x1 205 #define MX8ULP_PAD_PTD18__EXT_AUD_MCLK3 0x0048 0x0B14 0x5 0x3 227 #define MX8ULP_PAD_PTD20__LPSPI4_SIN 0x0050 0x0908 0x3 0x1 239 #define MX8ULP_PAD_PTD21__LPSPI4_SOUT 0x0054 0x090C 0x3 0x1 252 #define MX8ULP_PAD_PTD22__LPSPI4_SCK 0x0058 0x0904 0x3 0x1 264 #define MX8ULP_PAD_PTD23__LPSPI4_PCS0 0x005C 0x08F4 0x3 0x1 275 #define MX8ULP_PAD_PTE0__SPDIF_IN3 0x0080 0x0B80 0x3 0x2 278 #define MX8ULP_PAD_PTE0__TPM8_CLKIN 0x0080 0x0B30 0x6 0x3 [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_1_enum.h | 31 DBG_BLOCK_ID_PDMA = 0x3, 288 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 410 DBG_BLOCK_ID_SQ_BY4 = 0x3, 472 DBG_BLOCK_ID_CP0_BY8 = 0x3, 504 DBG_BLOCK_ID_MCD_BY16 = 0x3, 521 ENDIAN_8IN64 = 0x3, 527 ARRAY_1D_TILED_THICK = 0x3, 545 CONFIG_8_PIPE = 0x3, 559 CONFIG_8KB_ROW = 0x3, 569 CONFIG_1KB_SWAPS = 0x3, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_8_2_enum.h | 31 DBG_BLOCK_ID_PDMA = 0x3, 288 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 410 DBG_BLOCK_ID_SQ_BY4 = 0x3, 472 DBG_BLOCK_ID_CP0_BY8 = 0x3, 504 DBG_BLOCK_ID_MCD_BY16 = 0x3, 521 ENDIAN_8IN64 = 0x3, 527 ARRAY_1D_TILED_THICK = 0x3, 545 CONFIG_8_PIPE = 0x3, 559 CONFIG_8KB_ROW = 0x3, 569 CONFIG_1KB_SWAPS = 0x3, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/ |
H A D | smu_8_0_enum.h | 31 DBG_BLOCK_ID_PDMA = 0x3, 288 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 410 DBG_BLOCK_ID_SQ_BY4 = 0x3, 472 DBG_BLOCK_ID_CP0_BY8 = 0x3, 504 DBG_BLOCK_ID_MCD_BY16 = 0x3, 521 ENDIAN_8IN64 = 0x3, 527 ARRAY_1D_TILED_THICK = 0x3, 545 CONFIG_8_PIPE = 0x3, 559 CONFIG_8KB_ROW = 0x3, 569 CONFIG_1KB_SWAPS = 0x3, [all...] |
/linux-master/sound/soc/amd/include/ |
H A D | acp_2_2_enum.h | 31 DBG_BLOCK_ID_PDMA = 0x3, 288 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 410 DBG_BLOCK_ID_SQ_BY4 = 0x3, 472 DBG_BLOCK_ID_CP0_BY8 = 0x3, 504 DBG_BLOCK_ID_MCD_BY16 = 0x3, 521 ENDIAN_8IN64 = 0x3, 527 ARRAY_1D_TILED_THICK = 0x3, 545 CONFIG_8_PIPE = 0x3, 559 CONFIG_8KB_ROW = 0x3, 569 CONFIG_1KB_SWAPS = 0x3, [all...] |
/linux-master/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6sl-pinfunc.h | 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 24 #define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 32 #define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 39 #define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 47 #define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 54 #define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 61 #define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 68 #define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 75 #define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 82 #define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 [all...] |
H A D | imx53-pinfunc.h | 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 65 #define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 73 #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 81 #define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 88 #define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 119 #define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 126 #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 133 #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 140 #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 147 #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 [all...] |
/linux-master/scripts/dtc/include-prefixes/arm/nxp/imx/ |
H A D | imx6sl-pinfunc.h | 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 24 #define MX6SL_PAD_AUD_RXC__FEC_TX_CLK 0x050 0x2a8 0x70c 0x3 0x0 32 #define MX6SL_PAD_AUD_RXD__FEC_RX_ER 0x054 0x2ac 0x708 0x3 0x0 39 #define MX6SL_PAD_AUD_RXFS__FEC_MDIO 0x058 0x2b0 0x6f4 0x3 0x0 47 #define MX6SL_PAD_AUD_TXC__FEC_RX_DV 0x05c 0x2b4 0x704 0x3 0x0 54 #define MX6SL_PAD_AUD_TXD__FEC_TX_DATA0 0x060 0x2b8 0x000 0x3 0x0 61 #define MX6SL_PAD_AUD_TXFS__FEC_RX_DATA1 0x064 0x2bc 0x6fc 0x3 0x0 68 #define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR0 0x068 0x358 0x000 0x3 0x0 75 #define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x06c 0x35c 0x000 0x3 0x0 82 #define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x070 0x360 0x000 0x3 [all...] |
H A D | imx53-pinfunc.h | 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 65 #define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 73 #define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 81 #define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 88 #define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 119 #define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 126 #define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 133 #define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 140 #define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 147 #define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 [all...] |
/linux-master/arch/mips/include/asm/mach-au1x00/ |
H A D | au1xxx_dbdma.h | 114 #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */ 115 #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */ 117 #define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */ 124 #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ 233 #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) 234 #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) 241 #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) 249 #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) 254 #define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */ 262 #define DSCR_CMD1_FL(x) (((x) & 0x3) << 2 [all...] |
/linux-master/drivers/net/ethernet/broadcom/ |
H A D | cnic_defs.h | 256 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 272 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 622 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) 624 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) 638 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) 640 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) 642 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) 730 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 732 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 750 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<1 [all...] |
/linux-master/arch/arm64/kvm/hyp/nvhe/ |
H A D | host.S | 20 /* Store the host regs x2 and x3 */ 21 stp x2, x3, [x0, #CPU_XREG_OFFSET(2)] 24 ldp x2, x3, [sp], #16 // x0, x1 27 stp x2, x3, [x0, #CPU_XREG_OFFSET(0)] 79 ldp x2, x3, [x29, #CPU_XREG_OFFSET(2)] 135 mov x4, x3 136 mov x3, x2 137 hyp_pa x3, x6 226 mrs x3, par_el1 277 ldp x2, x3, [x1 [all...] |