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65bc25b8 |
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19-Jul-2023 |
Matus Gajdos <matuszpd@gmail.com> |
ASoC: fsl_spdif: Add support for 22.05 kHz sample rate Add support for 22.05 kHz sample rate for TX. Signed-off-by: Matus Gajdos <matuszpd@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20230719163154.19492-1-matuszpd@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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638cec39 |
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15-Mar-2022 |
Shengjiu Wang <shengjiu.wang@nxp.com> |
ASoC: fsl_spdif: Add new registers included on i.MX8ULP There are some new registers added on i.MX8ULP, they are the SPDIF transmit Professional C channel registers, 192bit SPDIF receive C channel registers, and 192bit SPDIF transmit C channel registers. There are two output lines, SPDIF_OUT1 and SPDIF_OUT2, the original REG_SPDIF_STCSCH and REG_SPDIF_STCSCL are used for SPDIF_OUT1, the new REG_SPDIF_STCSPH and REG_SPDIF_STCSPL are used for SPDIF_OUT2, the 192bit SPDIF C channel registers are used for both. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1647408538-2982-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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604e5178 |
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26-Apr-2021 |
Viorel Suman <viorel.suman@nxp.com> |
ASoC: fsl_spdif: add support for enabling raw capture mode Since i.MX8MM SPDIF interface is able to capture raw data. Add support in SPDIF driver for this functionality. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1619425444-8666-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1bfa3eaa |
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12-Oct-2020 |
Shengjiu Wang <shengjiu.wang@nxp.com> |
ASoC: fsl_spdif: Add support for higher sample rates Add 88200Hz and 176400Hz sample rates support for TX. Add 88200Hz, 176400Hz, 192000Hz sample rates support for RX. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/1602557360-18795-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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30c498a1 |
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18-Feb-2019 |
Viorel Suman <viorel.suman@nxp.com> |
ASoC: fsl_spdif: fix TXCLK_DF mask According to RM SPDIF TXCLK_DF mask is 7-bit wide. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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165a30e4 |
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01-May-2018 |
Fabio Estevam <fabio.estevam@nxp.com> |
ASoC: fsl_spdif: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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c7dfeed1 |
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15-Jun-2014 |
Anssi Hannula <anssi.hannula@iki.fi> |
ASoC: fsl_spdif: Add support for output sample rates 96kHz and 192kHz Add support for the output sample rates 96kHz and 192kHz. Tested with a Cubox-i imx6 system and an Onkyo TX-SR607 receiver. Signed-off-by: Anssi Hannula <anssi.hannula@iki.fi> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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f3a30baa |
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06-May-2014 |
Nicolin Chen <Guangyu.Chen@freescale.com> |
ASoC: fsl_spdif: Improve coding style 1) Apply better indentations 2) Drop braces for single statement. 3) Use simpler ternary to reduce code. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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e41a4a79 |
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30-Apr-2014 |
Nicolin Chen <Guangyu.Chen@freescale.com> |
ASoC: fsl_spdif: Rename all _div to _df We should have used _df by following the reference manual at the beginning. So this patch just renames them. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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9c6344b3 |
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30-Apr-2014 |
Nicolin Chen <Guangyu.Chen@freescale.com> |
ASoC: fsl_spdif: Use clk_set_rate() for spdif root clock only The clock mux for the Freescale S/PDIF controller has eight clock sources while most of them are from other moudles and even system clocks that do not allow a rate-changing operation. So we here only allow the clk_set_rate() and clk_round_rate() happened to spdif root clock, the private clock for S/PDIF controller. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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6ae66982 |
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18-Apr-2014 |
Nicolin Chen <Guangyu.Chen@freescale.com> |
ASoC: fsl_spdif: Fix wrong OFFSET of STC_SYSCLK_DIV It should use STC_SYSCLK_DIV_OFFSET. Thus fix it. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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a2388a49 |
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20-Aug-2013 |
Nicolin Chen <b42378@freescale.com> |
ASoC: fsl: Add S/PDIF CPU DAI driver This patch implements a device-tree-only CPU DAI driver for Freescale S/PDIF controller that supports stereo playback and record feature. Signed-off-by: Nicolin Chen <b42378@freescale.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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