Searched refs:x3 (Results 201 - 225 of 4324) sorted by relevance

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/linux-master/include/linux/mfd/
H A Dmax5970.h36 #define MAX5970_MON_MASK 0x3
50 #define MAX5970_VAL2REG_L(x) ((x) & 0x3)
61 #define STATUS1_PROT_MASK 0x3
69 #define MAX5970_IRNG_MASK 0x3
/linux-master/include/uapi/linux/
H A Dpcitest.h16 #define PCITEST_MSI _IOW('P', 0x3, int)
H A Dfirewire-constants.h43 #define EXTCODE_FETCH_ADD 0x3
74 #define SCODE_800 0x3
77 #define SCODE_BETA 0x3
/linux-master/include/asm-generic/bitops/
H A D__ffs.h35 if ((word & 0x3) == 0) {
/linux-master/tools/include/asm-generic/bitops/
H A D__ffs.h36 if ((word & 0x3) == 0) {
/linux-master/arch/sh/kernel/
H A Dio.c24 (((u32)to & 0x1f) == 0) && (((u32)from & 0x3) == 0)) {
58 if ((((u32)to | (u32)from) & 0x3) == 0) {
81 if ((((u32)to | (u32)from) & 0x3) == 0) {
/linux-master/arch/sparc/include/asm/
H A Dsfp-machine_32.h108 #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
120 : "%rJ" ((USItype)(x3)), \
133 #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
145 : "%rJ" ((USItype)(x3)), \
160 #define __FP_FRAC_DEC_4(x3,x2,x1,x0,y3,y2,y1,y0) __FP_FRAC_SUB_4(x3,x2,x1,x0,x3,x2,x1,x0,y3,y2,y1,y0)
162 #define __FP_FRAC_ADDI_4(x3,x2,x1,x0,i) \
167 : "=&r" (x3), \
172 "0" ((USItype)(x3)), \
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/linux-master/arch/arm/mach-omap2/
H A Dctrl_module_wkup_44xx.h65 #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
73 #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
83 #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
H A Dprm-regbits-44xx.h42 #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
53 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
55 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
/linux-master/arch/mips/include/asm/mach-ath79/
H A Dar933x_uart.h25 #define AR933X_UART_CS_PARITY_M 0x3
30 #define AR933X_UART_CS_IF_MODE_M 0x3
35 #define AR933X_UART_CS_FLOW_CTRL_M 0x3
/linux-master/drivers/devfreq/event/
H A Dexynos-nocp.h60 #define NOCP_CNT_SRC_INTEVENT_XFER_MASK (0x3 << NOCP_CNT_SRC_INTEVENT_SHIFT)
69 #define NOCP_CNT_ALARM_MODE_MASK (0x3 << NOCP_CNT_ALARM_MODE_SHIFT)
73 #define NOCP_CNT_ALARM_MODE_MIN_MAX_MASK (0x3 << NOCP_CNT_ALARM_MODE_SHIFT)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h42 #define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
44 #define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
49 #define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
54 #define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
59 #define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
64 #define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
70 #define GRPH_DEPTH(x) (((x) & 0x3) << 0)
92 #define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
99 #define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
100 #define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 1
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/linux-master/include/soc/at91/
H A Dsama7-ddr.h58 #define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
/linux-master/include/uapi/sound/
H A Dsnd_ar_tokens.h17 #define APM_SUB_GRAPH_SID_VOICE_CALL 0x3
24 #define APM_CONTAINER_CAP_ID_EP 0x3
33 #define APM_CONT_GRAPH_POS_STR_DEV 0x3
/linux-master/drivers/gpu/drm/i915/
H A Dintel_mchbar_regs.h102 #define BXT_DRAM_RANK_MASK 0x3
104 #define BXT_DRAM_RANK_DUAL 0x3
105 #define BXT_DRAM_WIDTH_MASK (0x3 << 4)
110 #define BXT_DRAM_WIDTH_X64 (0x3 << 4)
116 #define BXT_DRAM_SIZE_12GBIT (0x3 << 6)
133 #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0)
143 #define MAD_DIMM_ECC_MASK (0x3 << 24)
147 #define MAD_DIMM_ECC_ON (0x3 << 24)
165 #define SKL_DRAM_WIDTH_MASK (0x3 << 8)
176 #define ICL_DRAM_WIDTH_MASK (0x3 <<
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/linux-master/include/drm/
H A Di915_drm.h51 #define SNB_GMCH_GGMS_MASK 0x3
55 #define BDW_GMCH_GGMS_MASK 0x3
71 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
/linux-master/drivers/parisc/
H A Diosapic_private.h61 ** 0x3 corresponds to INT_D#
94 #define IRT_PO_MASK 0x3
98 #define IRT_EL_MASK 0x3
103 #define IRT_IRQ_MASK 0x3
/linux-master/sound/soc/codecs/
H A Dnau8540.h98 #define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT)
110 #define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)
113 #define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT)
118 #define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT)
141 #define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT)
145 #define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT)
146 #define NAU8540_I2S_DF_MASK 0x3
150 #define NAU8540_I2S_DF_PCM_AB 0x3
155 #define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)
182 #define NAU8540_ADC_OSR_MASK 0x3
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H A Dtscs454.h18 #define R_IRQMASK VIRT_ADDR(0x0, 0x3)
70 #define R_HSDSTAT VIRT_ADDR(0x1, 0x3)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
126 #define R_SPKEQFILT VIRT_ADDR(0x3, 0x1)
127 #define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
128 #define R_SPKCRWDM VIRT_ADDR(0x3, 0x3)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
130 #define R_SPKCRRDL VIRT_ADDR(0x3, 0x5)
131 #define R_SPKCRRDM VIRT_ADDR(0x3,
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H A Drt5645.h307 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
309 #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
311 #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
315 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
317 #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)
319 #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
369 #define RT5645_MONO_DMIC_R_SRC_MASK (0x3)
377 #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
382 #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
383 #define RT5645_DAC1_L_SEL_MASK (0x3 <<
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H A Drt5668.h425 #define RT5668_EXT_JD_SRC_JDL (0x3 << 4)
427 #define RT5668_JACK_TYPE_MASK (0x3)
433 #define RT5668_SEL_SHT_MID_TON_MASK (0x3 << 12)
453 #define RT5668_STO1_ADC_L_BST_MASK (0x3 << 14)
455 #define RT5668_STO1_ADC_R_BST_MASK (0x3 << 12)
477 #define RT5668_STO1_ADCL_SRC_MASK (0x3 << 10)
493 #define RT5668_STO1_ADCR_SRC_MASK (0x3 << 2)
533 #define RT5668_DAC_L1_SRC_MASK (0x3 << 4)
535 #define RT5668_DAC_R1_SRC_MASK (0x3)
539 #define RT5668_IF2_ADC_SEL_MASK (0x3 <<
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H A Drt5682s.h453 #define RT5682S_SEL_FAST_OFF_MASK (0x3 << 9)
497 #define RT5682S_EXT_JD_SRC_JDL (0x3 << 4)
499 #define RT5682S_JACK_TYPE_MASK (0x3)
508 #define RT5682S_SEL_SHT_MID_TON_MASK (0x3 << 12)
520 #define RT5682S_JD_FAST_OFF_SRC_GPIO4 (0x3 << 8)
538 #define RT5682S_STO1_ADC_L_BST_MASK (0x3 << 14)
540 #define RT5682S_STO1_ADC_R_BST_MASK (0x3 << 12)
562 #define RT5682S_STO1_ADCL_SRC_MASK (0x3 << 10)
572 #define RT5682S_STO1_ADCR_SRC_MASK (0x3 << 2)
614 #define RT5682S_IF2_DAC_SEL_MASK (0x3 <<
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H A Dda7219.h158 #define DA7219_MIC_1_AMP_IN_SEL_MASK (0x3 << 0)
191 #define DA7219_CIF_I2C_ADDR_CFG_MASK (0x3 << 0)
199 #define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2)
204 #define DA7219_PLL_MODE_MASK (0x3 << 6)
231 #define DA7219_DAI_L_SRC_MASK (0x3 << 0)
233 #define DA7219_DAI_R_SRC_MASK (0x3 << 4)
238 #define DA7219_DAI_BCLKS_PER_WCLK_MASK (0x3 << 0)
242 #define DA7219_DAI_BCLKS_PER_WCLK_256 (0x3 << 0)
256 #define DA7219_DAI_FORMAT_MASK (0x3 << 0)
260 #define DA7219_DAI_FORMAT_DSP (0x3 <<
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/linux-master/arch/arm64/kvm/hyp/
H A Daarch32.c82 it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
121 itbits |= (cpsr & (0x3 << 25)) >> 25;
132 cpsr |= (itbits & 0x3) << 25;
/linux-master/include/linux/qed/
H A Dfcoe_common.h19 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
169 #define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
171 #define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
173 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
229 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
231 #define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
233 #define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
236 #define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
238 #define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
240 #define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
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