/linux-master/sound/soc/codecs/ |
H A D | inno_rk3036.h | 42 #define INNO_R02_DACM_MSK (0x3 << 3) 43 #define INNO_R02_DACM_PCM (0x3 << 3) /*DAC Mode*/ 47 #define INNO_R02_VWL_MSK (0x3 << 5) 48 #define INNO_R02_VWL_32BIT (0x3 << 5) /*1/2Frame Valid Word Len*/ 62 #define INNO_R03_FWL_MSK (0x3 << 2) 63 #define INNO_R03_FWL_32BIT (0x3 << 2) /*1/2Frame Word Length*/ 94 #define INNO_R09_HP_ANTIPOP_MSK 0x3
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H A D | nau8825.h | 112 /* CLK_DIVIDER (0x3) */ 118 #define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT) 120 #define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT) 133 #define NAU8825_FLL_CLK_SRC_MASK (0x3 << NAU8825_FLL_CLK_SRC_SFT) 136 #define NAU8825_FLL_CLK_SRC_FS (0x3 << NAU8825_FLL_CLK_SRC_SFT) 140 #define NAU8825_FLL_REF_DIV_MASK (0x3 << NAU8825_FLL_REF_DIV_SFT) 232 #define NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK (0x3 << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT) 247 #define NAU8825_TDM_DACL_RX_MASK (0x3 << NAU8825_TDM_DACL_RX_SFT) 249 #define NAU8825_TDM_DACR_RX_MASK (0x3 << NAU8825_TDM_DACR_RX_SFT) 250 #define NAU8825_TDM_TX_MASK 0x3 [all...] |
H A D | rt5616.h | 218 #define RT5616_ADC_L_BST_MASK (0x3 << 14) 220 #define RT5616_ADC_R_BST_MASK (0x3 << 12) 222 #define RT5616_ADC_COMP_MASK (0x3 << 10) 314 #define RT5616_DAC_L2_SEL_MASK (0x3 << 14) 319 #define RT5616_DAC_L2_SEL_BASS (0x3 << 14) 320 #define RT5616_DAC_R2_SEL_MASK (0x3 << 12) 333 #define RT5616_RXDC_SEL_MASK (0x3 << 8) 338 #define RT5616_RXDC_SEL_SWAP (0x3 << 8) 339 #define RT5616_RXDP_SEL_MASK (0x3 << 6) 344 #define RT5616_RXDP_SEL_SWAP (0x3 << [all...] |
H A D | rt5682.h | 440 #define RT5682_EXT_JD_SRC_JDL (0x3 << 4) 442 #define RT5682_JACK_TYPE_MASK (0x3) 448 #define RT5682_SEL_SHT_MID_TON_MASK (0x3 << 12) 468 #define RT5682_STO1_ADC_L_BST_MASK (0x3 << 14) 470 #define RT5682_STO1_ADC_R_BST_MASK (0x3 << 12) 492 #define RT5682_STO1_ADCL_SRC_MASK (0x3 << 10) 508 #define RT5682_STO1_ADCR_SRC_MASK (0x3 << 2) 548 #define RT5682_DAC_L1_SRC_MASK (0x3 << 4) 550 #define RT5682_DAC_R1_SRC_MASK (0x3) 554 #define RT5682_IF2_ADC_SEL_MASK (0x3 << [all...] |
H A D | rt5514.h | 137 #define RT5514_I2S_DF_PCM_B (0x3 << 16) 138 #define RT5514_TDMSLOT_SEL_RX_MASK (0x3 << 10) 142 #define RT5514_TDMSLOT_SEL_RX_8CH (0x3 << 10) 143 #define RT5514_CH_LEN_RX_MASK (0x3 << 8) 148 #define RT5514_CH_LEN_RX_32 (0x3 << 8) 149 #define RT5514_TDMSLOT_SEL_TX_MASK (0x3 << 6) 153 #define RT5514_TDMSLOT_SEL_TX_8CH (0x3 << 6) 154 #define RT5514_CH_LEN_TX_MASK (0x3 << 4) 159 #define RT5514_CH_LEN_TX_32 (0x3 << 4) 160 #define RT5514_I2S_DL_MASK (0x3 << [all...] |
H A D | rt5640.h | 197 #define RT5640_ID_MASK (0x3 << 1) 200 #define RT5640_ID_5642 (0x3 << 1) 257 #define RT5640_ADC_L_BST_MASK (0x3 << 14) 259 #define RT5640_ADC_R_BST_MASK (0x3 << 12) 261 #define RT5640_ADC_COMP_MASK (0x3 << 10) 273 #define RT5640_ADC_2_SRC_MASK (0x3 << 10) 292 #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10) 305 #define RT5640_MONO_ADC_R2_SRC_MASK (0x3 << 2) 398 #define RT5640_DAC_L2_SEL_MASK (0x3 << 14) 403 #define RT5640_DAC_L2_SEL_BASS (0x3 << 1 [all...] |
/linux-master/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | cpu_ca53_cfg_masks.h | 24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3 42 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 62 #define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK 0x3 76 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK 0x3 116 #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK 0x3 144 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK 0x3 164 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK 0x3
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/linux-master/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt7621.c | 10 #define MT7621_GPIO_MODE_UART3_MASK 0x3 13 #define MT7621_GPIO_MODE_UART2_MASK 0x3 17 #define MT7621_GPIO_MODE_WDT_MASK 0x3 22 #define MT7621_GPIO_MODE_PCIE_MASK 0x3 25 #define MT7621_GPIO_MODE_MDIO_MASK 0x3 30 #define MT7621_GPIO_MODE_SPI_MASK 0x3 33 #define MT7621_GPIO_MODE_SDHCI_MASK 0x3
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/linux-master/drivers/power/supply/ |
H A D | max8998_charger.c | 132 max8998_update_reg(i2c, MAX8998_REG_CHGR1, 0x1 << 3, 0x3 << 3); 135 max8998_update_reg(i2c, MAX8998_REG_CHGR1, 0x0 << 3, 0x3 << 3); 138 max8998_update_reg(i2c, MAX8998_REG_CHGR1, 0x2 << 3, 0x3 << 3); 141 max8998_update_reg(i2c, MAX8998_REG_CHGR1, 0x3 << 3, 0x3 << 3); 155 max8998_update_reg(i2c, MAX8998_REG_CHGR2, 0x0 << 4, 0x3 << 4); 158 max8998_update_reg(i2c, MAX8998_REG_CHGR2, 0x1 << 4, 0x3 << 4); 161 max8998_update_reg(i2c, MAX8998_REG_CHGR2, 0x2 << 4, 0x3 << 4); 164 max8998_update_reg(i2c, MAX8998_REG_CHGR2, 0x3 << 4, 0x3 << [all...] |
/linux-master/drivers/edac/ |
H A D | mce_amd.h | 19 #define TT(x) (((x) >> 2) & 0x3) 21 #define II(x) (((x) >> 2) & 0x3) 23 #define LL(x) ((x) & 0x3) 27 #define PP(x) (((x) >> 9) & 0x3) 29 #define UU(x) (((x) >> 8) & 0x3)
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/linux-master/sound/soc/rockchip/ |
H A D | rockchip_pdm.h | 57 #define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x)) 72 #define PDM_CLK_2560FS (0x3 << 0) 74 #define PDM_CIC_RATIO_MSK (0x3 << 0) 79 #define PDM_HPF_CF_MSK (0x3 << 0) 83 #define PDM_HPF_493HZ (0x3 << 0)
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/linux-master/arch/arm/mach-imx/ |
H A D | crmregs-imx3.h | 61 #define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18) 63 #define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21) 65 #define MXC_CCM_CCMR_LPM_MASK (0x3 << 14) 68 #define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11) 75 #define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1) 88 #define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6) 95 #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 118 #define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1) 160 #define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30) 171 #define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 2 [all...] |
/linux-master/drivers/soc/tegra/cbb/ |
H A D | tegra194-cbb.c | 223 [0x3] = "AON", 280 [0x3] = "ccroc_p2ps/I/ccroc_p2ps", 299 [0x3] = "cbb_firewall/T/cbb_firewall", 405 { 0x0, 0x3, 0x00, 0x0, 0x02340000, 0, 0x00000000 }, 515 [0x3] = "cvc_i/I/0", 573 { 0x0, 0x04, 0x3, 0x0, 0x20a00000, 0, 0x00000000 }, 580 { 0x0, 0x08, 0x3, 0x0, 0x0d0a0000, 2, 0x00040000 }, 590 { 0x0, 0x0e, 0x3, 0x0, 0x0d180000, 3, 0x00030000 }, 600 { 0x0, 0x10, 0x3, 0x0, 0x0d220000, 3, 0x00030000 }, 610 { 0x0, 0x17, 0x3, [all...] |
/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | icp_qat_hw_20_comp_defs.h | 29 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK 0x3 35 ICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3, 75 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK 0x3 81 ICP_QAT_HW_COMP_20_LBMS_LBMS_4MB = 0x3, 144 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6 = 0x3, 158 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4S = 0x3, 253 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK 0x3 259 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_4MB = 0x3, 271 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4S = 0x3,
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/linux-master/drivers/usb/phy/ |
H A D | phy-fsl-usb.h | 14 #define USB_CMD_ASP (0x3<<8) 24 #define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) 28 #define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) 34 #define USB_CMD_ASP_11 (0x3<<8) 87 #define PORTSC_LINE_STATUS_BITS (0x3<<10) 89 #define PORTSC_PORT_INDICTOR_CTRL (0x3<<14) 96 #define PORTSC_PORT_SPEED_MASK (0x3<<26) 98 #define PORTSC_PHY_TYPE_SEL (0x3<<30) 103 #define PORTSC_LINE_STATUS_UNDEF (0x3<<10) 110 #define PORTSC_PIC_UNDEF (0x3<<1 [all...] |
/linux-master/drivers/gpu/drm/radeon/ |
H A D | evergreen_reg.h | 62 # define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0) 66 # define EVERGREEN_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 71 # define EVERGREEN_GRPH_Z(x) (((x) & 0x3) << 4) 72 # define EVERGREEN_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 96 # define EVERGREEN_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 109 # define EVERGREEN_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 122 # define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 127 # define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 132 # define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 137 # define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << [all...] |
/linux-master/arch/powerpc/boot/dts/ |
H A D | kuroboxHD.dts | 132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1 133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1 137 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 140 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 141 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1 142 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1 143 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
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H A D | kuroboxHG.dts | 132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1 133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1 137 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 140 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 141 0x7000 0x0 0x0 0x2 &mpic 0x3 0x1 142 0x7000 0x0 0x0 0x3 &mpic 0x3 0x1 143 0x7000 0x0 0x0 0x4 &mpic 0x3 0x1
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/linux-master/scripts/dtc/include-prefixes/dt-bindings/usb/ |
H A D | pd.h | 12 #define PDO_TYPE_MASK 0x3 65 #define PDO_APDO_TYPE_MASK 0x3 134 | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21 \ 209 (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \ 231 (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \ 342 (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18 \ 343 | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10 \ 344 | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5 \ 348 | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 1 [all...] |
/linux-master/include/dt-bindings/usb/ |
H A D | pd.h | 12 #define PDO_TYPE_MASK 0x3 65 #define PDO_APDO_TYPE_MASK 0x3 134 | (is_modal) << 26 | ((dfp) & 0x7) << 23 | ((conn) & 0x3) << 21 \ 209 (((ver) & 0x7) << 29 | ((cap) & 0xf) << 24 | ((conn) & 0x3) << 22 \ 231 (((ver) & 0x7) << 29 | ((cap) & 0x7) << 24 | ((conn) & 0x3) << 22 \ 342 (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18 \ 343 | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 | (tx1d) << 10 \ 344 | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 | ((cur) & 0x3) << 5 \ 348 | ((conn) & 0x3) << 18 | ((lat) & 0xf) << 13 | ((term) & 0x3) << 1 [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_11_0_enum.h | 39 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3, 81 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3, 137 CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3, 177 CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3, 195 CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3, 213 CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3, 240 CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3, 262 CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3, 288 CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3, 314 CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3, [all...] |
/linux-master/arch/arm64/boot/dts/freescale/ |
H A D | imx8mp-pinfunc.h | 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 [all...] |
/linux-master/scripts/dtc/include-prefixes/arm64/freescale/ |
H A D | imx8mp-pinfunc.h | 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vce/ |
H A D | vce_3_0_sh_mask.h | 94 #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3 96 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3 98 #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3 103 #define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x3 107 #define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x3 111 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x3
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/linux-master/drivers/net/wireless/ath/ath9k/ |
H A D | reg_wow.h | 127 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) 129 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) 131 #define AR_WOW_LEN3_SHIFT(_i) ((0xb - ((_i) & 0xb)) << 0x3) 133 #define AR_WOW_LEN4_SHIFT(_i) ((0xf - ((_i) & 0xf)) << 0x3)
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