/linux-master/arch/arm64/kvm/hyp/ |
H A D | hyp-entry.S | 19 /* x0 and x1 were saved in the vector entry */ 39 ldp x0, x1, [sp], #16 56 * restoring x1, as it can be clobbered anyway. 58 ldr x1, [sp] // Guest's x0 78 get_vcpu_ptr x1, x0 84 get_vcpu_ptr x1, x0 89 get_vcpu_ptr x1, x0 108 get_vcpu_ptr x1, x0 155 stp x0, x1, [sp, #-16]! 172 stp x0, x1, [s [all...] |
/linux-master/tools/testing/selftests/bpf/ |
H A D | ip_check_defrag_frags.h | 10 0x45, 0x0, 0x0, 0x2c, 0x0, 0x1, 0x20, 0x0, 0x40, 0x11, 11 0xac, 0xe8, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8, 17 0x45, 0x0, 0x0, 0x2c, 0x0, 0x1, 0x20, 0x3, 0x40, 0x11, 18 0xac, 0xe5, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8, 24 0x45, 0x0, 0x0, 0x1e, 0x0, 0x1, 0x0, 0x6, 0x40, 0x11, 25 0xcc, 0xf0, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8, 31 0x0, 0x0, 0x1, 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 33 0x11, 0x0, 0x0, 0x1, 0x0, 0x0, 0xbe, 0xef, 0xbe, 0xee, 41 0x0, 0x0, 0x1, 0x0, 0xfc, 0x0, 0x0, 0x0, 0x0, 0x0, 51 0x0, 0x0, 0x1, [all...] |
/linux-master/drivers/net/wireless/realtek/rtw88/ |
H A D | coex.h | 8 #define COEX_CCK_2 0x1 9 #define COEX_RESP_ACK_BY_WL_FW 0x1 17 #define COEX_RF_ON 0x1 20 #define PARA1_H2C69_DIS_5MS 0x1 25 #define PARA1_H2C69_TDMA_2SLOT 0x1 115 COEX_GNT_SET_SW_LOW = 0x1, 211 COEX_IPS_ENTER = 0x1, 216 COEX_LPS_ENABLE = 0x1, 259 COEX_WL_TPUT_RX = 0x1, 277 COEX_CSETUP_ANT_SWITCH = 0x1, [all...] |
/linux-master/include/linux/mfd/ |
H A D | rohm-bd71828.h | 146 #define BD71828_GPIO_OUT_HI 0x1 148 #define BD71828_GPIO_OUT_MASK 0x1 339 #define BD71828_INT_BUCK1_OCP_MASK 0x1 348 #define BD71828_INT_DCIN_DET_MASK 0x1 353 #define BD71828_INT_DCIN_MON_RES_MASK 0x1 362 #define BD71828_INT_VSYS_UV_RES_MASK 0x1 371 #define BD71828_INT_CHG_DCIN_ILIM_MASK 0x1 380 #define BD71828_INT_BAT_TEMP_NORMAL_MASK 0x1 396 #define BD71828_INT_BAT_MON_RES_MASK 0x1 399 #define BD71828_INT_BAT_CC_MON1_MASK 0x1 [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
H A D | dpcs_3_1_4_sh_mask.h | 34 #define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 59 #define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT 0x1 77 #define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT 0x1 95 #define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 125 #define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT 0x1 181 #define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT 0x1 211 #define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT 0x1 267 #define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT 0x1 295 #define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT 0x1 331 #define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT 0x1 [all...] |
/linux-master/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
H A D | dcore0_edma0_qm_masks.h | 49 #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 97 #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 135 #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 141 #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 179 #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 229 #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 267 #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 365 #define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 383 #define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 389 #define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 [all...] |
H A D | pdma0_qm_masks.h | 49 #define PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 97 #define PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 135 #define PDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 141 #define PDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 179 #define PDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 229 #define PDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 267 #define PDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 365 #define PDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 383 #define PDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 389 #define PDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_3_0_1_enum.h | 28 DC_IH_SRC_ID_START = 0x1, 55 IH_PERF_SEL_IDLE = 0x1, 97 SEM_PERF_SEL_IDLE = 0x1, 273 SRBM_PERF_SEL_BIF_BUSY = 0x1, 302 GRBM_GFX_INDEX_SDMA0 = 0x1, 319 SRBM_GFX_CNTL_SDMA0 = 0x1, 336 SDMA_PERF_SEL_IDLE = 0x1, 425 DBG_BLOCK_ID_DBG = 0x1, 682 DBG_BLOCK_ID_VMC_BY2 = 0x1, 804 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, [all...] |
H A D | oss_3_0_enum.h | 28 DC_IH_SRC_ID_START = 0x1, 55 IH_PERF_SEL_IDLE = 0x1, 208 SRBM_PERF_SEL_BIF_BUSY = 0x1, 237 GRBM_GFX_INDEX_SDMA0 = 0x1, 254 SRBM_GFX_CNTL_SDMA0 = 0x1, 271 SDMA_PERF_SEL_IDLE = 0x1, 328 ENDIAN_8IN16 = 0x1, 334 ARRAY_LINEAR_ALIGNED = 0x1, 352 CONFIG_2_PIPE = 0x1, 358 CONFIG_8_BANK = 0x1, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gca/ |
H A D | gfx_8_1_enum.h | 29 NUMBER_SNORM = 0x1, 39 SWAP_ALT = 0x1, 45 CB_NORMAL = 0x1, 54 ROUND_TRUNCATE = 0x1, 58 EXPORT_4C_16BPC = 0x1, 64 BLEND_ONE = 0x1, 87 COMB_SRC_MINUS_DST = 0x1, 94 FORCE_OPT_DISABLE = 0x1, 104 CMASK_CLR00_F1 = 0x1, 122 CMASK_ADDR_LINEAR = 0x1, [all...] |
H A D | gfx_8_0_enum.h | 29 NUMBER_SNORM = 0x1, 39 SWAP_ALT = 0x1, 45 CB_NORMAL = 0x1, 54 ROUND_TRUNCATE = 0x1, 58 EXPORT_4C_16BPC = 0x1, 64 BLEND_ONE = 0x1, 87 COMB_SRC_MINUS_DST = 0x1, 94 FORCE_OPT_DISABLE = 0x1, 104 CMASK_CLR00_F1 = 0x1, 122 CMASK_ADDR_LINEAR = 0x1, [all...] |
/linux-master/arch/loongarch/include/asm/ |
H A D | loongarch.h | 24 #define REG_RA 0x1 62 #define LOONGARCH_CPUCFG1 0x1 196 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT) 204 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT) 206 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT) 208 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT) 217 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */ 219 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT) 221 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT) 228 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIF [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_gpu_commands.h | 69 #define MI_OVERLAY_ON (0x1<<21) 205 #define SC_UPDATE_SCISSOR (0x1<<1) 206 #define SC_ENABLE_MASK (0x1<<0) 207 #define SC_ENABLE (0x1<<0) 209 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 216 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 253 #define TILE_X 0x1 254 #define XMAJOR 0x1 402 ((0x3 << 29) | (0x0 << 27) | (0x1 << 24) | (0x1 << 1 [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/ |
H A D | link_dp_training_fixed_vs_pe_retimer.c | 77 const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF}; 78 uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0}; 79 uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0}; 194 const uint8_t vendor_lttpr_write_data_reset[4] = {0x1, 0x50, 0x63, 0xFF}; 197 const uint8_t vendor_lttpr_write_data_intercept_en[4] = {0x1, 0x55, 0x63, 0x0}; 198 const uint8_t vendor_lttpr_write_data_intercept_dis[4] = {0x1, 0x55, 0x63, 0x6E}; 199 const uint8_t vendor_lttpr_write_data_adicora_eq1[4] = {0x1, 0x55, 0x63, 0x2E}; 200 const uint8_t vendor_lttpr_write_data_adicora_eq2[4] = {0x1, 0x55, 0x63, 0x01}; 201 const uint8_t vendor_lttpr_write_data_adicora_eq3[4] = {0x1, 0x55, 0x63, 0x68}; 203 uint8_t vendor_lttpr_write_data_vs[4] = {0x1, [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_4_2_sh_mask.h | 41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 51 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 54 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 109 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 112 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 123 #define UVD_CGC_GATE__SYS_MASK 0x1 126 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 163 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 166 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 [all...] |
H A D | uvd_3_1_sh_mask.h | 41 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 44 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 51 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 54 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 109 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 112 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 123 #define UVD_CGC_GATE__SYS_MASK 0x1 126 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 163 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 166 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 [all...] |
/linux-master/arch/arm64/kernel/ |
H A D | efi-rt-wrapper.S | 18 stp x1, x18, [sp, #16] 43 mov x1, x3 53 ldp x1, x2, [sp, #16]
|
/linux-master/drivers/gpu/drm/vmwgfx/ |
H A D | vmwgfx_msg_arm64.h | 56 register u64 x1 asm("x1") = in_ebx; 68 : "+r"(x0), "+r"(x1), "+r"(x2), 73 *ebx = x1; 89 register u64 x1 asm("x1") = cmd; 101 : "+r"(x0), "+r"(x1), "+r"(x2), 106 *ebx = x1;
|
/linux-master/sound/soc/codecs/ |
H A D | rt712-sdca.h | 114 #define RT712_HIDDEN_REG_SW_RESET (0x1 << 14) 117 #define RT712_COMBOJACK_AUTO_DET_STATUS (0x1 << 11) 118 #define RT712_COMBOJACK_AUTO_DET_TRS (0x1 << 10) 119 #define RT712_COMBOJACK_AUTO_DET_CTIA (0x1 << 9) 120 #define RT712_COMBOJACK_AUTO_DET_OMTP (0x1 << 8) 123 #define RT712_DAC_DC_CALI_TRIGGER (0x1 << 15)
|
/linux-master/tools/testing/selftests/powerpc/pmu/sampling_tests/ |
H A D | misc.h | 73 return ((mmcr0 >> 7) & 0x1); 78 return ((mmcr0 >> 8) & 0x1); 83 return ((mmcr0 >> 14) & 0x1); 88 return ((mmcr0 >> 15) & 0x1); 93 return ((mmcr0 >> 27) & 0x1); 231 return mmcra & 0x1;
|
/linux-master/include/linux/mlx5/ |
H A D | mlx5_ifc_vdpa.h | 9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1, 31 u8 full_emulation[0x1]; 32 u8 virtio_version_1_0[0x1]; 93 u8 dirty_bitmap_dump_enable[0x1]; 157 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1, 172 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1,
|
/linux-master/drivers/media/platform/nxp/ |
H A D | imx-pxp.h | 46 #define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1 79 #define BV_PXP_CTRL_ROTATE1__ROT_90 0x1 93 #define BV_PXP_CTRL_ROTATE0__ROT_90 0x1 186 #define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 347 #define BV_PXP_PS_CTRL_DECX__DECX2 0x1 355 #define BV_PXP_PS_CTRL_DECY__DECY2 0x1 499 #define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1 519 #define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1 534 #define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1 653 #define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1 [all...] |
/linux-master/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_5_0_sh_mask.h | 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 38 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 39 #define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1 41 #define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1 44 #define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1 69 #define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1 72 #define CONFIG_CNTL__VGA_DIS__SHIFT 0x1 81 #define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1 95 #define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1 99 #define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1 [all...] |
/linux-master/arch/sh/kernel/vsyscall/ |
H A D | vsyscall-sigreturn.S | 45 .byte 0x1 /* Version number */ 47 .uleb128 0x1 /* Code alignment factor */ 50 .uleb128 0x1 /* Augmentation length and data */
|
/linux-master/arch/arm/mach-sunxi/ |
H A D | headsmp.S | 38 orr r1, r1, #(0x1 << 31) 44 orr r1, r1, #(0x1 << 26) 46 orr r1, r1, #(0x1<<3)
|