Searched refs:x1 (Results 226 - 250 of 5699) sorted by relevance

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/linux-master/include/uapi/sound/
H A Dsnd_ar_tokens.h6 #define APM_SUB_GRAPH_PERF_MODE_LOW_POWER 0x1
9 #define APM_SUB_GRAPH_DIRECTION_TX 0x1
13 #define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
20 #define APM_CONTAINER_CAP_ID_PP 0x1
29 #define APM_CONT_GRAPH_POS_STREAM 0x1
37 #define APM_PROC_DOMAIN_ID_MDSP 0x1
/linux-master/tools/testing/selftests/arm64/fp/
H A Dzt-test.S33 // x1: generation
59 // x1: generation
65 ldr x1, =scratch
76 // bytes starting at address x1.
82 stp x0, x1, [sp, #-0x20]!
87 ldrb w4, [x1, x5]
95 ldp x0, x1, [sp], #0x20
107 mov x1, #ZT_B
114 ldr x1, =scratch
168 // x1
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H A Dza-test.S34 // Trivial memory copy: copy x2 bytes, starting at address x1, to address x0.
39 0: ldrb w3, [x1], #1
48 // x1: row in ZA
84 // x1: row number
88 mov x12, x1 // Use x12 for vector select
93 ldr x1, =scratch
102 // bytes starting at address x1.
108 stp x0, x1, [sp, #-0x20]!
113 ldrb w4, [x1, x5]
121 ldp x0, x1, [s
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/linux-master/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h36 #define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */
37 #define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */
38 #define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */
39 #define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */
40 #define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */
41 #define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */
42 #define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */
43 #define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */
44 #define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */
45 #define REG_PRE_BIT2POS CRA(0x7,0x1,
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/linux-master/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Drot0_masks.h25 #define ROT0_KMD_MODE_EN_MASK 0x1
29 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
71 #define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1
75 #define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1
105 #define ROT0_WBC_INFO_EMPTY_MASK 0x1
111 #define ROT0_WBC_MON_CNT_MASK 0x1
125 #define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1
153 #define ROT0_RSB_INFO_EMPTY_MASK 0x1
173 #define ROT0_MSS_SEI_STATUS_I0_MASK 0x1
223 #define ROT0_MSS_SPI_STATUS_I0_MASK 0x1
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H A Dpsoc_global_conf_masks.h29 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
33 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
73 #define PSOC_GLOBAL_CONF_QSPI_SPI_SEL_MASK 0x1
77 #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SPI_MASK 0x1
83 #define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1
87 #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1
91 #define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1
117 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1
137 #define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1
141 #define PSOC_GLOBAL_CONF_QSPI_SPI_BOOTSEQ_RST_VAL_MASK 0x1
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H A Ddcore0_vdec0_brdg_ctrl_masks.h25 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
41 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
51 #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1
103 #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1
125 #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1
139 #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1
159 #define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1
163 #define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1
167 #define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1
171 #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1
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H A Dpcie_vdec0_brdg_ctrl_masks.h25 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
41 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
51 #define PCIE_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1
103 #define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1
125 #define PCIE_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1
139 #define PCIE_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1
159 #define PCIE_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1
163 #define PCIE_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1
167 #define PCIE_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1
171 #define PCIE_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1
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H A Ddcore0_tpc0_cfg_masks.h33 #define DCORE0_TPC0_CFG_STALL_ON_ERR_V_MASK 0x1
37 #define DCORE0_TPC0_CFG_CLK_EN_LBW_CFG_DIS_MASK 0x1
43 #define DCORE0_TPC0_CFG_IQ_RL_EN_V_MASK 0x1
63 #define DCORE0_TPC0_CFG_IQ_LBW_CLK_EN_V_MASK 0x1
71 #define DCORE0_TPC0_CFG_TPC_LOCK_LOCK_MASK 0x1
75 #define DCORE0_TPC0_CFG_CGU_SB_TSB_DISABLE_MASK 0x1
79 #define DCORE0_TPC0_CFG_CGU_CNT_DCACHE_DISABLE_MASK 0x1
129 #define DCORE0_TPC0_CFG_CGU_CPE_NEARBYINT_DISABLE_MASK 0x1
171 #define DCORE0_TPC0_CFG_FP16_FTZ_IN_MODE_MASK 0x1
175 #define DCORE0_TPC0_CFG_DCACHE_CFG_G_PREF_DIS_MASK 0x1
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/linux-master/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dtpc0_eml_cfg_masks.h24 #define TPC0_EML_CFG_DBG_CNT_DBG_ENTER_MASK 0x1
42 #define TPC0_EML_CFG_DBG_STS_DBG_MODE_MASK 0x1
74 #define TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_MASK 0x1
108 #define TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_MASK 0x1
134 #define TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_MASK 0x1
168 #define TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_MASK 0x1
202 #define TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_MASK 0x1
236 #define TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_MASK 0x1
258 #define TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_MASK 0x1
280 #define TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_MASK 0x1
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/linux-master/sound/soc/codecs/
H A Dnau8822.h86 /* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
88 #define NAU8822_REFIMP_80K 0x1
91 #define NAU8822_IOBUF_EN (0x1 << 2)
92 #define NAU8822_ABIAS_EN (0x1 << 3)
93 #define NAU8822_PLL_EN_MASK (0x1 << 5)
94 #define NAU8822_PLL_ON (0x1 << 5)
100 #define NAU8822_WLEN_20 (0x1 << 5)
103 #define NAU8822_LRP_MASK (0x1 << 7)
104 #define NAU8822_BCLKP_MASK (0x1 << 8)
112 #define NAU8822_CLKIOEN_MASK 0x1
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H A Drt711.h171 #define RT711_DAC_DC_CALI_TRIGGER (0x1 << 15)
174 #define RT711_JD2_DIGITAL_JD_MODE_SEL (0x1 << 1)
176 #define RT711_JD2_2_JD_MODE (0x1 << 1)
179 #define RT711_JD2_2PORT_200K_DECODE_HP (0x1 << 13)
180 #define RT711_JD2_2PORT_100K_DECODE (0x1 << 12)
183 #define RT711_HP_JD_SEL_JD2 (0x1 << 1)
186 #define RT711_JD2_1PORT_JD_HP (0x1 << 10)
188 #define RT711_JD1_2PORT_TYPE_100K_DECODE (0x1 << 0)
190 #define RT711_JD1_2PORT_JD_LINE1 (0x1 << 0)
193 #define RT711_JD2_PAD_PULL_UP_MASK (0x1 <<
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/linux-master/drivers/pinctrl/berlin/
H A Dberlin-bg2cd.c22 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
27 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
32 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
39 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
47 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
55 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
63 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
66 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
70 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
73 BERLIN_PINCTRL_FUNCTION(0x1, "spi
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/linux-master/include/linux/qed/
H A Deth_common.h107 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
109 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
111 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
113 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
115 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
117 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
119 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
121 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
131 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
133 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
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/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_register.h11 #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
19 #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
21 #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
23 #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
32 #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
34 #define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
36 #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
56 #define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
58 #define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)
60 #define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIF
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/linux-master/drivers/gpu/drm/xe/instructions/
H A Dxe_gfxpipe_commands.h13 #define PIPELINE_SINGLE_DW REG_FIELD_PREP(GFXPIPE_PIPELINE, 0x1)
45 #define STATE_BASE_ADDRESS GFXPIPE_COMMON_CMD(0x1, 0x1)
46 #define STATE_SIP GFXPIPE_COMMON_CMD(0x1, 0x2)
47 #define GPGPU_CSR_BASE_ADDRESS GFXPIPE_COMMON_CMD(0x1, 0x4)
48 #define STATE_COMPUTE_MODE GFXPIPE_COMMON_CMD(0x1, 0x5)
49 #define CMD_3DSTATE_BTD GFXPIPE_COMMON_CMD(0x1, 0x6)
50 #define STATE_SYSTEM_MEM_FENCE_ADDRESS GFXPIPE_COMMON_CMD(0x1, 0x9)
51 #define STATE_CONTEXT_DATA_BASE_ADDRESS GFXPIPE_COMMON_CMD(0x1, 0xB)
55 #define PIPELINE_SELECT GFXPIPE_SINGLE_DW_CMD(0x1,
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/linux-master/drivers/net/ethernet/atheros/atlx/
H A Datl2.h127 #define DMAR_EN 0x1 /* 1: Enable DMAR */
135 #define DMAW_EN 0x1
231 #define TX_PKT_HEADER_INS_VLAN_MASK 0x1
258 #define TX_PKT_STATUS_OK_MASK 0x1
260 #define TX_PKT_STATUS_BCAST_MASK 0x1
262 #define TX_PKT_STATUS_MCAST_MASK 0x1
264 #define TX_PKT_STATUS_PAUSE_MASK 0x1
266 #define TX_PKT_STATUS_CTRL_MASK 0x1
268 #define TX_PKT_STATUS_DEFER_MASK 0x1
270 #define TX_PKT_STATUS_EXC_DEFER_MASK 0x1
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/linux-master/drivers/pinctrl/sunxi/
H A Dpinctrl-sun20i-d1.c20 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x1, "gpio_out"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
118 SUNXI_FUNCTION(0x1, "gpio_ou
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/linux-master/include/drm/
H A Ddrm_rect.h38 * @x1: horizontal starting coordinate (inclusive)
47 int x1, y1, x2, y2; member in struct:drm_rect
61 .x1 = (x), \
74 #define DRM_RECT_ARG(r) drm_rect_width(r), drm_rect_height(r), (r)->x1, (r)->y1
90 (r)->x1 >> 16, (((r)->x1 & 0xffff) * 15625) >> 10, \
104 r->x1 = x;
124 r->x1 -= dw >> 1;
141 r->x1 += dx;
158 drm_rect_translate(r, x - r->x1,
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_2_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
33 #define VCE_VCPU_CNTL__CLK_EN_MASK 0x1
49 #define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x1
71 #define VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK 0x1
74 #define VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT 0x1
101 #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x1
/linux-master/sound/soc/qcom/
H A Dlpass-hdmi.h14 #define LPASS_HDMITX_LEGACY_ENABLE 0x1
17 #define LPASS_DATA_FORMAT_SHIFT 0x1
20 #define LPASS_DATA_FORMAT_NON_LINEAR 0x1
24 #define LPASS_TX_CTL_RESET 0x1
38 #define REPLACE_VBIT 0x1
40 #define NON_LINEAR_PCM_DATA 0x1
41 #define HDMITX_PARITY_CALC_EN 0x1
/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_enum.h29 DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
49 DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
57 DCIO_UNIPHYB_FBDIV_CLK = 0x1,
65 DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
73 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
81 DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
99 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
117 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
123 DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
129 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
[all...]
/linux-master/arch/mips/include/asm/pci/
H A Dbridge.h403 #define BRIDGE_REV_A 0x1
412 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
413 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
418 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
419 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
420 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
423 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
424 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
425 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
426 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 2
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/linux-master/crypto/
H A Dserpent_generic.c27 #define loadkeys(x0, x1, x2, x3, i) \
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
30 #define storekeys(x0, x1, x2, x3, i) \
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
33 #define store_and_load_keys(x0, x1, x2, x3, s, l) \
34 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
36 #define K(x0, x1, x2, x3, i) ({ \
38 x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
41 #define LK(x0, x1, x
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/linux-master/arch/x86/events/intel/
H A Dknc.c127 INTEL_EVENT_CONSTRAINT(0xc3, 0x1), /* HWP_L2HIT */
128 INTEL_EVENT_CONSTRAINT(0xc4, 0x1), /* HWP_L2MISS */
129 INTEL_EVENT_CONSTRAINT(0xc8, 0x1), /* L2_READ_HIT_E */
130 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* L2_READ_HIT_M */
131 INTEL_EVENT_CONSTRAINT(0xca, 0x1), /* L2_READ_HIT_S */
132 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* L2_READ_MISS */
133 INTEL_EVENT_CONSTRAINT(0xcc, 0x1), /* L2_WRITE_HIT */
134 INTEL_EVENT_CONSTRAINT(0xce, 0x1), /* L2_STRONGLY_ORDERED_STREAMING_VSTORES_MISS */
135 INTEL_EVENT_CONSTRAINT(0xcf, 0x1), /* L2_WEAKLY_ORDERED_STREAMING_VSTORE_MISS */
136 INTEL_EVENT_CONSTRAINT(0xd7, 0x1), /* L2_VICTIM_REQ_WITH_DAT
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