Searched refs:x1 (Results 176 - 200 of 5701) sorted by relevance

1234567891011>>

/linux-master/arch/arm64/kernel/
H A Dreloc_test_syms.S64 adr x1, 0f
65 ldr x0, [x1]
66 add x0, x0, x1
72 adr x1, 0f
73 ldr w0, [x1]
74 add x0, x0, x1
80 adr x1, 0f
81 ldrsh w0, [x1]
82 add x0, x0, x1
/linux-master/arch/x86/crypto/
H A Dserpent-sse2-x86_64-asm_64.S41 #define S0_1(x0, x1, x2, x3, x4) \
47 pxor x1, x3; \
48 pand x0, x1; \
49 pxor x4, x1; \
51 #define S0_2(x0, x1, x2, x3, x4) \
55 pand x1, x2; \
57 pxor RNOT, x1; \
59 pxor x2, x1;
61 #define S1_1(x0, x1, x2, x3, x4) \
62 movdqa x1, x
[all...]
/linux-master/drivers/net/ethernet/cisco/enic/
H A Dcq_enet_desc.h39 #define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)
40 #define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)
41 #define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)
42 #define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)
55 #define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14)
60 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)
61 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)
66 #define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK (0x1 << 12)
80 #define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0)
81 #define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 <<
[all...]
/linux-master/sound/soc/atmel/
H A Datmel-pdmic.h9 #define PDMIC_CR_SWRST 0x1
14 #define PDMIC_CR_ENPDM_EN 0x1
21 #define PDMIC_MR_CLKS_GCK 0x1
43 #define PDMIC_DSPR0_HPFBYP_DIS 0x1
48 #define PDMIC_DSPR0_SINBYP_DIS 0x1
54 #define PDMIC_DSPR0_SIZE_32_BITS 0x1
59 #define PDMIC_DSPR0_OSR_64 0x1
/linux-master/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h28 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30)
33 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28)
37 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26)
47 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22)
52 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
57 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
62 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
67 #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14)
126 #define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
138 #define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 2
[all...]
/linux-master/arch/arm64/lib/
H A Dmte.S31 multitag_transfer_size x1, x2
33 add x0, x0, x1
47 mrs x1, dczid_el0
48 tbnz x1, #4, 2f // Branch if DC GZVA is prohibited
51 lsl x1, x2, x1
54 add x0, x0, x1
68 * x1 - address of the source page
72 mov x3, x1
87 * x1
[all...]
/linux-master/sound/soc/codecs/
H A Drt1305.h103 #define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15)
106 #define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15)
112 #define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10)
117 #define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8)
124 #define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11)
126 #define RT1305_PLL_1_M_BYPASS (0x1 << 11)
134 #define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15)
137 #define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15)
143 #define RT1305_I2S_DF_SEL_LEFT (0x1 << 12)
149 #define RT1305_I2S_DL_SEL_20B (0x1 << 1
[all...]
/linux-master/include/dt-bindings/pinctrl/
H A Dat91.h18 #define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
26 #define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
31 #define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9)
/linux-master/scripts/dtc/include-prefixes/dt-bindings/pinctrl/
H A Dat91.h18 #define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8)
26 #define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
31 #define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9)
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddalsmc.h30 #define DALSMC_VERSION 0x1
33 #define DALSMC_Result_OK 0x1
42 #define DALSMC_MSG_TestMessage 0x1
/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss-csid-gen2.h13 #define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
29 #define ENCODE_FORMAT_RAW_8_BIT 0x1
36 #define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM, UNCOMPRESSED_10/16_BIT */
/linux-master/drivers/pinctrl/sunxi/
H A Dpinctrl-sun50i-a100-r.c19 SUNXI_FUNCTION(0x1, "gpio_out"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x1, "gpio_ou
[all...]
H A Dpinctrl-sun8i-a23-r.c28 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
75 SUNXI_FUNCTION(0x1, "gpio_ou
[all...]
H A Dpinctrl-sun8i-h3-r.c21 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
41 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x1, "gpio_ou
[all...]
H A Dpinctrl-sun50i-a100.c19 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x1, "gpio_out"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x1, "gpio_ou
[all...]
/linux-master/arch/arm64/include/asm/
H A Del2_setup.h53 __check_hvhe .LnVHE_\@, x1
61 mrs x1, id_aa64dfr0_el1
62 ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 variable
72 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 variable
88 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 variable
105 mrs x1, id_aa64mmfr1_el1
106 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 variable
141 mrs x1, mpidr_el1 variable
143 msr vmpidr_el2, x1
148 __check_hvhe .LnVHE_\@, x1
161 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 variable
162 cbz x1, .Lskip_fgt_\\@ variable
165 mrs x1, id_aa64dfr0_el1 variable
166 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 variable
167 cmp x1, #3 variable
177 mrs x1, id_aa64pfr1_el1 variable
178 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 variable
179 cbz x1, .Lset_pie_fgt_\\@ variable
187 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 variable
188 cbz x1, .Lset_fgt_\\@ variable
199 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU variable
200 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 variable
201 cbz x1, .Lskip_fgt_\\@ variable
273 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\\@, .Lskip_sve_\\@, x1, x2 variable
294 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\\@, .Lskip_sme_\\@, x1, x2 variable
313 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps variable
320 mrs_s x1, SYS_ID_AA64SMFR0_EL1 variable
321 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\\@, .Lskip_sme_fa64_\\@, x1, x2 variable
329 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\\@, .Lskip_sme_zt0_\\@, x1, x2 variable
337 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? variable
338 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 variable
339 cbz x1, .Lskip_sme_\\@ variable
[all...]
/linux-master/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
32 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
33 #define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
39 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
40 #define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
46 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
53 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1
[all...]
H A Dimx6sll-pinfunc.h16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
27 #define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0
34 #define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0
40 #define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0
42 #define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1
45 #define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0
47 #define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1
50 #define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1
[all...]
/linux-master/scripts/dtc/include-prefixes/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
32 #define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0
33 #define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1
39 #define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0
40 #define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1
46 #define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0
53 #define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1
[all...]
H A Dimx6sll-pinfunc.h16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
27 #define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0
34 #define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0
40 #define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0
42 #define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1
45 #define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0
47 #define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1
50 #define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1
[all...]
/linux-master/drivers/scsi/fnic/
H A Dcq_enet_desc.h38 #define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)
39 #define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)
40 #define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)
41 #define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)
54 #define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14)
59 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)
60 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)
70 #define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0)
71 #define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 << 0)
72 #define CQ_ENET_RQ_DESC_FLAGS_UDP (0x1 <<
[all...]
/linux-master/sound/soc/samsung/
H A Dpcm.c37 #define S3C_PCM_CTL_TXDMA_EN (0x1 << 6)
38 #define S3C_PCM_CTL_RXDMA_EN (0x1 << 5)
39 #define S3C_PCM_CTL_TXMSB_AFTER_FSYNC (0x1 << 4)
40 #define S3C_PCM_CTL_RXMSB_AFTER_FSYNC (0x1 << 3)
41 #define S3C_PCM_CTL_TXFIFO_EN (0x1 << 2)
42 #define S3C_PCM_CTL_RXFIFO_EN (0x1 << 1)
43 #define S3C_PCM_CTL_ENABLE (0x1 << 0)
46 #define S3C_PCM_CLKCTL_SERCLK_EN (0x1 << 19)
47 #define S3C_PCM_CLKCTL_SERCLKSEL_PCLK (0x1 << 18)
54 #define S3C_PCM_TXFIFO_DVALID (0x1 << 1
[all...]
/linux-master/arch/powerpc/boot/dts/
H A DkuroboxHD.dts130 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
131 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
135 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
136 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
[all...]
H A DkuroboxHG.dts130 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
131 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
135 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
136 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
[all...]
/linux-master/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-init.S53 * x1: struct kvm_nvhe_init_params PA
68 1: mov x0, x1
87 ldr x1, [x0, #NVHE_INIT_STACK_HYP_VA]
88 mov sp, x1
90 ldr x1, [x0, #NVHE_INIT_MAIR_EL2]
91 msr mair_el2, x1
93 ldr x1, [x0, #NVHE_INIT_HCR_EL2]
94 msr hcr_el2, x1
97 and x2, x1, x2
109 ldr x1, [x
[all...]

Completed in 208 milliseconds

1234567891011>>