/linux-master/drivers/irqchip/ |
H A D | irq-sa11x0.c | 40 writel_relaxed(reg, iobase + ICMR); 49 writel_relaxed(reg, iobase + ICMR); 100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); 110 writel_relaxed(st->iccr, iobase + ICCR); 111 writel_relaxed(st->iclr, iobase + ICLR); 113 writel_relaxed(st->icmr, iobase + ICMR); 155 writel_relaxed(0, iobase + ICMR); 158 writel_relaxed(0, iobase + ICLR); 164 writel_relaxed(1, iobase + ICCR);
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/linux-master/drivers/clocksource/ |
H A D | asm9260_timer.c | 113 writel_relaxed(delta, priv.base + HW_MR0); 115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); 122 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); 136 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), 146 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), 149 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); 151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); 173 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); 217 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); 219 writel_relaxed(BM_PR_DISABL [all...] |
H A D | clksrc_st_lpc.c | 32 writel_relaxed(0, ddata.base + LPC_LPT_START_OFF); 33 writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF); 34 writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF); 35 writel_relaxed(1, ddata.base + LPC_LPT_START_OFF);
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H A D | timer-davinci.c | 82 writel_relaxed(val, clockevent->base + reg); 99 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); 112 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); 205 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); 206 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34); 207 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); 222 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); 223 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12); 224 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); 230 writel_relaxed( [all...] |
/linux-master/arch/arm/mach-qcom/ |
H A D | platsmp.c | 70 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); 71 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); 72 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); 171 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); 177 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); 179 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); 184 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); 189 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); 194 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); 199 writel_relaxed(va [all...] |
/linux-master/drivers/rtc/ |
H A D | rtc-rtd119x.c | 61 writel_relaxed(val, data->base + RTD_RTCCR); 76 writel_relaxed(0x5a, data->base + RTD_RTCEN); 78 writel_relaxed(0, data->base + RTD_RTCEN); 145 writel_relaxed((tm->tm_sec << 1) & RTD_RTCSEC_RTCSEC_MASK, data->base + RTD_RTCSEC); 146 writel_relaxed(tm->tm_min & RTD_RTCMIN_RTCMIN_MASK, data->base + RTD_RTCMIN); 147 writel_relaxed(tm->tm_hour & RTD_RTCHR_RTCHR_MASK, data->base + RTD_RTCHR); 148 writel_relaxed(day & RTD_RTCDATE1_RTCDATE1_MASK, data->base + RTD_RTCDATE1); 149 writel_relaxed((day >> 8) & RTD_RTCDATE2_RTCDATE2_MASK, data->base + RTD_RTCDATE2); 195 writel_relaxed(RTD_RTCACR_RTCPWR, data->base + RTD_RTCACR); 199 writel_relaxed( [all...] |
H A D | rtc-st-lpc.c | 59 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); 61 writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF); 62 writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF); 63 writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF); 65 writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF); 114 writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF); 115 writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF); 116 writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF); 265 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); 266 writel_relaxed( [all...] |
H A D | rtc-sa1100.c | 57 writel_relaxed(0, info->rtsr); 64 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr); 73 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr); 79 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr); 105 writel_relaxed(rtsr, info->rtsr); 122 writel_relaxed(rtc_tm_to_time64(tm), info->rcnr); 143 writel_relaxed(readl_relaxed(info->rtsr) & 145 writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar); 147 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr); 149 writel_relaxed(readl_relaxe [all...] |
/linux-master/drivers/gpio/ |
H A D | gpio-sa1100.c | 50 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); 69 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); 82 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); 122 writel_relaxed(grer, base + R_GRER); 123 writel_relaxed(gfer, base + R_GFER); 158 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); 242 writel_relaxed(mask, gedr); 263 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER); 264 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER); 269 writel_relaxed(readl_relaxe [all...] |
H A D | gpio-rda.c | 60 writel_relaxed(tmp, base + reg); 75 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); 98 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); 102 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); 108 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); 112 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); 119 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); 123 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_CLR); 132 writel_relaxed(value, base + RDA_GPIO_INT_CTRL_SET); 141 writel_relaxed(valu [all...] |
/linux-master/drivers/video/fbdev/mmp/hw/ |
H A D | mmp_ctrl.c | 42 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); 126 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); 139 writel_relaxed(win->pitch[0], 141 writel_relaxed(win->pitch[2] << 16 | win->pitch[1], 144 writel_relaxed((win->ysrc << 16) | win->xsrc, 146 writel_relaxed((win->ydst << 16) | win->xdst, 148 writel_relaxed(win->ypos << 16 | win->xpos, 151 writel_relaxed(win->pitch[0], (void __iomem *)®s->g_pitch); 153 writel_relaxed((win->ysrc << 16) | win->xsrc, 155 writel_relaxed((wi [all...] |
H A D | mmp_spi.c | 38 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); 42 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); 45 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); 48 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); 74 writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL); 76 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); 100 writel_relaxed(IOPAD_DUMB18SPI |
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/linux-master/arch/arm/mach-omap2/ |
H A D | omap4-common.c | 83 writel_relaxed(0, dram_sync); 118 writel_relaxed(readl_relaxed(dram_sync), dram_sync); 119 writel_relaxed(readl_relaxed(sram_sync), sram_sync); 177 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL); 183 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL); 203 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); 205 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER); 207 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
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/linux-master/drivers/clk/mxs/ |
H A D | clk-pll.c | 36 writel_relaxed(1 << pll->power, pll->base + SET); 47 writel_relaxed(1 << pll->power, pll->base + CLR); 54 writel_relaxed(1 << 31, pll->base + CLR); 63 writel_relaxed(1 << 31, pll->base + SET);
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/linux-master/drivers/vfio/platform/reset/ |
H A D | vfio_platform_bcmflexrm.c | 40 writel_relaxed(0x0, ring + RING_CONTROL); 44 writel_relaxed(BIT(CONTROL_FLUSH_SHIFT), ring + RING_CONTROL); 56 writel_relaxed(0x0, ring + RING_CONTROL);
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/linux-master/drivers/media/platform/qcom/camss/ |
H A D | camss-csid-4-7.c | 225 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); 230 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); 234 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); 238 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); 249 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0); 254 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1); 264 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); 280 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); 284 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); 289 writel_relaxed(va [all...] |
H A D | camss-csid-4-1.c | 196 writel_relaxed(val, csid->base + CAMSS_CSID_TG_VC_CFG); 201 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_0(0)); 205 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_1(0)); 209 writel_relaxed(val, csid->base + CAMSS_CSID_TG_DT_n_CGG_2(0)); 220 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_0); 225 writel_relaxed(val, csid->base + CAMSS_CSID_CORE_CTRL_1); 234 writel_relaxed(val, csid->base + CAMSS_CSID_CID_LUT_VC_n(vc)); 240 writel_relaxed(val, csid->base + CAMSS_CSID_CID_n_CFG(cid)); 244 writel_relaxed(val, csid->base + CAMSS_CSID_TG_CTRL); 249 writel_relaxed(va [all...] |
H A D | camss-vfe-17x.c | 197 writel_relaxed(bits | set_bits, vfe->base + reg); 215 writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0); 220 writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD); 230 writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG); 233 writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER); 237 writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); 239 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); 243 writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC); 245 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm)); 248 writel_relaxed(va [all...] |
/linux-master/arch/arm/kernel/ |
H A D | smp_twd.c | 39 writel_relaxed(0, twd_base + TWD_TIMER_CONTROL); 46 writel_relaxed(TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT, 57 writel_relaxed(DIV_ROUND_CLOSEST(twd_timer_rate, HZ), 59 writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); 70 writel_relaxed(evt, twd_base + TWD_TIMER_COUNTER); 71 writel_relaxed(ctrl, twd_base + TWD_TIMER_CONTROL); 85 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT); 163 writel_relaxed(0x1, twd_base + TWD_TIMER_CONTROL); 166 writel_relaxed(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER); 229 writel_relaxed( [all...] |
/linux-master/drivers/gpu/drm/meson/ |
H A D | meson_osd_afbcd.c | 84 writel_relaxed(VIU_SW_RESET_OSD1_AFBCD, 86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); 103 writel_relaxed(FIELD_PREP(OSD1_AFBCD_ID_FIFO_THRD, 0x40) | 133 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); 135 writel_relaxed(FIELD_PREP(OSD1_AFBCD_HREG_VSIZE_IN, 141 writel_relaxed(priv->viu.osd1_addr >> 4, 143 writel_relaxed(priv->viu.osd1_addr >> 4, 146 writel_relaxed((0xe4 << 24) | (priv->viu.osd1_addr & 0xffffff), 162 writel_relaxed(conv_lbuf_len, 165 writel_relaxed(FIELD_PRE [all...] |
/linux-master/arch/arm/mach-imx/ |
H A D | gpc.c | 36 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 42 writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) | 48 writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN); 59 writel_relaxed(val, gpc_base + GPC_CNTR); 73 writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); 86 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 112 writel_relaxed(~0, reg_imr1 + i * 4); 122 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); 133 writel_relaxed(val, reg); 144 writel_relaxed(va [all...] |
/linux-master/drivers/mfd/ |
H A D | mcp-sa11x0.c | 53 writel_relaxed(m->mccr0, MCCR0(m)); 65 writel_relaxed(m->mccr0, MCCR0(m)); 81 writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); 108 writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); 130 writel_relaxed(m->mccr0, MCCR0(m)); 138 writel_relaxed(m->mccr0, MCCR0(m)); 208 writel_relaxed(-1, MCSR(m)); 209 writel_relaxed(m->mccr1, MCCR1(m)); 210 writel_relaxed(m->mccr0, MCCR0(m)); 272 writel_relaxed( [all...] |
/linux-master/drivers/usb/phy/ |
H A D | phy-tegra-usb.c | 230 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); 236 writel_relaxed(val, base + TEGRA_USB_PORTSC1); 251 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); 258 writel_relaxed(val, base + TEGRA_USB_PORTSC1); 352 writel_relaxed(val, base + UTMIP_BIAS_CFG0); 399 writel_relaxed(val, base + UTMIP_BIAS_CFG0); 433 writel_relaxed(val, base + USB_SUSP_CTRL); 439 writel_relaxed(val, base + USB_SUSP_CTRL); 466 writel_relaxed(val, base + USB_SUSP_CTRL); 472 writel_relaxed(va [all...] |
/linux-master/drivers/net/ethernet/hisilicon/ |
H A D | hix5hd2_gmac.c | 316 writel_relaxed(val, priv->ctrl_base); 319 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); 326 writel_relaxed(val, priv->base + PORT_MODE); 327 writel_relaxed(0, priv->base + MODE_CHANGE_EN); 328 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); 333 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); 334 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); 335 writel_relaxed(0, priv->base + RX_FQ_REG_EN); 337 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); 338 writel_relaxed(r [all...] |
/linux-master/drivers/thermal/ |
H A D | rockchip_thermal.c | 687 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 690 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 693 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); 694 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 696 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 698 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 728 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + 731 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, 733 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 735 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIM [all...] |