1// SPDX-License-Identifier: GPL-2.0
2/*
3 * camss-vfe-170.c
4 *
5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v170
6 *
7 * Copyright (C) 2020-2021 Linaro Ltd.
8 */
9
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/iopoll.h>
13
14#include "camss.h"
15#include "camss-vfe.h"
16
17#define VFE_HW_VERSION				(0x000)
18
19#define VFE_GLOBAL_RESET_CMD			(0x018)
20#define		GLOBAL_RESET_CMD_CORE		BIT(0)
21#define		GLOBAL_RESET_CMD_CAMIF		BIT(1)
22#define		GLOBAL_RESET_CMD_BUS		BIT(2)
23#define		GLOBAL_RESET_CMD_BUS_BDG	BIT(3)
24#define		GLOBAL_RESET_CMD_REGISTER	BIT(4)
25#define		GLOBAL_RESET_CMD_PM		BIT(5)
26#define		GLOBAL_RESET_CMD_BUS_MISR	BIT(6)
27#define		GLOBAL_RESET_CMD_TESTGEN	BIT(7)
28#define		GLOBAL_RESET_CMD_DSP		BIT(8)
29#define		GLOBAL_RESET_CMD_IDLE_CGC	BIT(9)
30#define		GLOBAL_RESET_CMD_RDI0		BIT(10)
31#define		GLOBAL_RESET_CMD_RDI1		BIT(11)
32#define		GLOBAL_RESET_CMD_RDI2		BIT(12)
33#define		GLOBAL_RESET_CMD_RDI3		BIT(13)
34#define		GLOBAL_RESET_CMD_VFE_DOMAIN	BIT(30)
35#define		GLOBAL_RESET_CMD_RESET_BYPASS	BIT(31)
36
37#define VFE_CORE_CFG				(0x050)
38#define		CFG_PIXEL_PATTERN_YCBYCR	(0x4)
39#define		CFG_PIXEL_PATTERN_YCRYCB	(0x5)
40#define		CFG_PIXEL_PATTERN_CBYCRY	(0x6)
41#define		CFG_PIXEL_PATTERN_CRYCBY	(0x7)
42#define		CFG_COMPOSITE_REG_UPDATE_EN	BIT(4)
43
44#define VFE_IRQ_CMD				(0x058)
45#define		CMD_GLOBAL_CLEAR		BIT(0)
46
47#define VFE_IRQ_MASK_0					(0x05c)
48#define		MASK_0_CAMIF_SOF			BIT(0)
49#define		MASK_0_CAMIF_EOF			BIT(1)
50#define		MASK_0_RDI_REG_UPDATE(n)		BIT((n) + 5)
51#define		MASK_0_IMAGE_MASTER_n_PING_PONG(n)	BIT((n) + 8)
52#define		MASK_0_IMAGE_COMPOSITE_DONE_n(n)	BIT((n) + 25)
53#define		MASK_0_RESET_ACK			BIT(31)
54
55#define VFE_IRQ_MASK_1					(0x060)
56#define		MASK_1_CAMIF_ERROR			BIT(0)
57#define		MASK_1_VIOLATION			BIT(7)
58#define		MASK_1_BUS_BDG_HALT_ACK			BIT(8)
59#define		MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n)	BIT((n) + 9)
60#define		MASK_1_RDI_SOF(n)			BIT((n) + 29)
61
62#define VFE_IRQ_CLEAR_0					(0x064)
63#define VFE_IRQ_CLEAR_1					(0x068)
64
65#define VFE_IRQ_STATUS_0				(0x06c)
66#define		STATUS_0_CAMIF_SOF			BIT(0)
67#define		STATUS_0_RDI_REG_UPDATE(n)		BIT((n) + 5)
68#define		STATUS_0_IMAGE_MASTER_PING_PONG(n)	BIT((n) + 8)
69#define		STATUS_0_IMAGE_COMPOSITE_DONE(n)	BIT((n) + 25)
70#define		STATUS_0_RESET_ACK			BIT(31)
71
72#define VFE_IRQ_STATUS_1				(0x070)
73#define		STATUS_1_VIOLATION			BIT(7)
74#define		STATUS_1_BUS_BDG_HALT_ACK		BIT(8)
75#define		STATUS_1_RDI_SOF(n)			BIT((n) + 27)
76
77#define VFE_VIOLATION_STATUS			(0x07c)
78
79#define VFE_CAMIF_CMD				(0x478)
80#define		CMD_CLEAR_CAMIF_STATUS		BIT(2)
81
82#define VFE_CAMIF_CFG				(0x47c)
83#define		CFG_VSYNC_SYNC_EDGE		(0)
84#define			VSYNC_ACTIVE_HIGH	(0)
85#define			VSYNC_ACTIVE_LOW	(1)
86#define		CFG_HSYNC_SYNC_EDGE		(1)
87#define			HSYNC_ACTIVE_HIGH	(0)
88#define			HSYNC_ACTIVE_LOW	(1)
89#define		CFG_VFE_SUBSAMPLE_ENABLE	BIT(4)
90#define		CFG_BUS_SUBSAMPLE_ENABLE	BIT(5)
91#define		CFG_VFE_OUTPUT_EN		BIT(6)
92#define		CFG_BUS_OUTPUT_EN		BIT(7)
93#define		CFG_BINNING_EN			BIT(9)
94#define		CFG_FRAME_BASED_EN		BIT(10)
95#define		CFG_RAW_CROP_EN			BIT(22)
96
97#define VFE_REG_UPDATE_CMD			(0x4ac)
98#define		REG_UPDATE_RDI(n)		BIT(1 + (n))
99
100#define VFE_BUS_IRQ_MASK(n)		(0x2044 + (n) * 4)
101#define VFE_BUS_IRQ_CLEAR(n)		(0x2050 + (n) * 4)
102#define VFE_BUS_IRQ_STATUS(n)		(0x205c + (n) * 4)
103#define		STATUS0_COMP_RESET_DONE		BIT(0)
104#define		STATUS0_COMP_REG_UPDATE0_DONE	BIT(1)
105#define		STATUS0_COMP_REG_UPDATE1_DONE	BIT(2)
106#define		STATUS0_COMP_REG_UPDATE2_DONE	BIT(3)
107#define		STATUS0_COMP_REG_UPDATE3_DONE	BIT(4)
108#define		STATUS0_COMP_REG_UPDATE_DONE(n)	BIT((n) + 1)
109#define		STATUS0_COMP0_BUF_DONE		BIT(5)
110#define		STATUS0_COMP1_BUF_DONE		BIT(6)
111#define		STATUS0_COMP2_BUF_DONE		BIT(7)
112#define		STATUS0_COMP3_BUF_DONE		BIT(8)
113#define		STATUS0_COMP4_BUF_DONE		BIT(9)
114#define		STATUS0_COMP5_BUF_DONE		BIT(10)
115#define		STATUS0_COMP_BUF_DONE(n)	BIT((n) + 5)
116#define		STATUS0_COMP_ERROR		BIT(11)
117#define		STATUS0_COMP_OVERWRITE		BIT(12)
118#define		STATUS0_OVERFLOW		BIT(13)
119#define		STATUS0_VIOLATION		BIT(14)
120/* WM_CLIENT_BUF_DONE defined for buffers 0:19 */
121#define		STATUS1_WM_CLIENT_BUF_DONE(n)		BIT(n)
122#define		STATUS1_EARLY_DONE			BIT(24)
123#define		STATUS2_DUAL_COMP0_BUF_DONE		BIT(0)
124#define		STATUS2_DUAL_COMP1_BUF_DONE		BIT(1)
125#define		STATUS2_DUAL_COMP2_BUF_DONE		BIT(2)
126#define		STATUS2_DUAL_COMP3_BUF_DONE		BIT(3)
127#define		STATUS2_DUAL_COMP4_BUF_DONE		BIT(4)
128#define		STATUS2_DUAL_COMP5_BUF_DONE		BIT(5)
129#define		STATUS2_DUAL_COMP_BUF_DONE(n)		BIT(n)
130#define		STATUS2_DUAL_COMP_ERROR			BIT(6)
131#define		STATUS2_DUAL_COMP_OVERWRITE		BIT(7)
132
133#define VFE_BUS_IRQ_CLEAR_GLOBAL		(0x2068)
134
135#define VFE_BUS_WM_DEBUG_STATUS_CFG		(0x226c)
136#define		DEBUG_STATUS_CFG_STATUS0(n)	BIT(n)
137#define		DEBUG_STATUS_CFG_STATUS1(n)	BIT(8 + (n))
138
139#define VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER	(0x2080)
140
141#define VFE_BUS_WM_ADDR_SYNC_NO_SYNC		(0x2084)
142#define		BUS_VER2_MAX_CLIENTS (24)
143#define		WM_ADDR_NO_SYNC_DEFAULT_VAL \
144				((1 << BUS_VER2_MAX_CLIENTS) - 1)
145
146#define VFE_BUS_WM_CGC_OVERRIDE			(0x200c)
147#define		WM_CGC_OVERRIDE_ALL		(0xFFFFF)
148
149#define VFE_BUS_WM_TEST_BUS_CTRL		(0x211c)
150
151#define VFE_BUS_WM_STATUS0(n)			(0x2200 + (n) * 0x100)
152#define VFE_BUS_WM_STATUS1(n)			(0x2204 + (n) * 0x100)
153#define VFE_BUS_WM_CFG(n)			(0x2208 + (n) * 0x100)
154#define		WM_CFG_EN			(0)
155#define		WM_CFG_MODE			(1)
156#define			MODE_QCOM_PLAIN	(0)
157#define			MODE_MIPI_RAW	(1)
158#define		WM_CFG_VIRTUALFRAME		(2)
159#define VFE_BUS_WM_HEADER_ADDR(n)		(0x220c + (n) * 0x100)
160#define VFE_BUS_WM_HEADER_CFG(n)		(0x2210 + (n) * 0x100)
161#define VFE_BUS_WM_IMAGE_ADDR(n)		(0x2214 + (n) * 0x100)
162#define VFE_BUS_WM_IMAGE_ADDR_OFFSET(n)		(0x2218 + (n) * 0x100)
163#define VFE_BUS_WM_BUFFER_WIDTH_CFG(n)		(0x221c + (n) * 0x100)
164#define		WM_BUFFER_DEFAULT_WIDTH		(0xFF01)
165
166#define VFE_BUS_WM_BUFFER_HEIGHT_CFG(n)		(0x2220 + (n) * 0x100)
167#define VFE_BUS_WM_PACKER_CFG(n)		(0x2224 + (n) * 0x100)
168
169#define VFE_BUS_WM_STRIDE(n)			(0x2228 + (n) * 0x100)
170#define		WM_STRIDE_DEFAULT_STRIDE	(0xFF01)
171
172#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n)	(0x2248 + (n) * 0x100)
173#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n)	(0x224c + (n) * 0x100)
174#define VFE_BUS_WM_FRAMEDROP_PERIOD(n)		(0x2250 + (n) * 0x100)
175#define VFE_BUS_WM_FRAMEDROP_PATTERN(n)		(0x2254 + (n) * 0x100)
176#define VFE_BUS_WM_FRAME_INC(n)			(0x2258 + (n) * 0x100)
177#define VFE_BUS_WM_BURST_LIMIT(n)		(0x225c + (n) * 0x100)
178
179static u32 vfe_hw_version(struct vfe_device *vfe)
180{
181	u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION);
182
183	u32 gen = (hw_version >> 28) & 0xF;
184	u32 rev = (hw_version >> 16) & 0xFFF;
185	u32 step = hw_version & 0xFFFF;
186
187	dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n",
188		gen, rev, step);
189
190	return hw_version;
191}
192
193static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
194{
195	u32 bits = readl_relaxed(vfe->base + reg);
196
197	writel_relaxed(bits | set_bits, vfe->base + reg);
198}
199
200static void vfe_global_reset(struct vfe_device *vfe)
201{
202	u32 reset_bits = GLOBAL_RESET_CMD_CORE		|
203			 GLOBAL_RESET_CMD_CAMIF		|
204			 GLOBAL_RESET_CMD_BUS		|
205			 GLOBAL_RESET_CMD_BUS_BDG	|
206			 GLOBAL_RESET_CMD_REGISTER	|
207			 GLOBAL_RESET_CMD_TESTGEN	|
208			 GLOBAL_RESET_CMD_DSP		|
209			 GLOBAL_RESET_CMD_IDLE_CGC	|
210			 GLOBAL_RESET_CMD_RDI0		|
211			 GLOBAL_RESET_CMD_RDI1		|
212			 GLOBAL_RESET_CMD_RDI2		|
213			 GLOBAL_RESET_CMD_RDI3;
214
215	writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0);
216
217	/* Make sure IRQ mask has been written before resetting */
218	wmb();
219
220	writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD);
221}
222
223static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
224{
225	u32 val;
226
227	/*Set Debug Registers*/
228	val = DEBUG_STATUS_CFG_STATUS0(1) |
229	      DEBUG_STATUS_CFG_STATUS0(7);
230	writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG);
231
232	/* BUS_WM_INPUT_IF_ADDR_SYNC_FRAME_HEADER */
233	writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER);
234
235	/* no clock gating at bus input */
236	val = WM_CGC_OVERRIDE_ALL;
237	writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
238
239	writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
240
241	/* if addr_no_sync has default value then config the addr no sync reg */
242	val = WM_ADDR_NO_SYNC_DEFAULT_VAL;
243	writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC);
244
245	writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
246
247	val = WM_BUFFER_DEFAULT_WIDTH;
248	writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm));
249
250	val = 0;
251	writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm));
252
253	val = 0;
254	writel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); // XXX 1 for PLAIN8?
255
256	/* Configure stride for RDIs */
257	val = WM_STRIDE_DEFAULT_STRIDE;
258	writel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm));
259
260	/* Enable WM */
261	val = 1 << WM_CFG_EN |
262	      MODE_MIPI_RAW << WM_CFG_MODE;
263	writel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm));
264}
265
266static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
267{
268	/* Disable WM */
269	writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
270}
271
272static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
273			  struct vfe_line *line)
274{
275	struct v4l2_pix_format_mplane *pix =
276		&line->video_out.active_fmt.fmt.pix_mp;
277	u32 stride = pix->plane_fmt[0].bytesperline;
278
279	writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
280	writel_relaxed(stride * pix->height, vfe->base + VFE_BUS_WM_FRAME_INC(wm));
281}
282
283static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
284{
285	vfe->reg_update |= REG_UPDATE_RDI(line_id);
286
287	/* Enforce ordering between previous reg writes and reg update */
288	wmb();
289
290	writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
291
292	/* Enforce ordering between reg update and subsequent reg writes */
293	wmb();
294}
295
296static inline void vfe_reg_update_clear(struct vfe_device *vfe,
297					enum vfe_line_id line_id)
298{
299	vfe->reg_update &= ~REG_UPDATE_RDI(line_id);
300}
301
302static void vfe_enable_irq_common(struct vfe_device *vfe)
303{
304	vfe_reg_set(vfe, VFE_IRQ_MASK_0, ~0u);
305	vfe_reg_set(vfe, VFE_IRQ_MASK_1, ~0u);
306
307	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(0));
308	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(1));
309	writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(2));
310}
311
312static void vfe_isr_halt_ack(struct vfe_device *vfe)
313{
314	complete(&vfe->halt_complete);
315}
316
317static void vfe_isr_read(struct vfe_device *vfe, u32 *status0, u32 *status1)
318{
319	*status0 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_0);
320	*status1 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_1);
321
322	writel_relaxed(*status0, vfe->base + VFE_IRQ_CLEAR_0);
323	writel_relaxed(*status1, vfe->base + VFE_IRQ_CLEAR_1);
324
325	/* Enforce ordering between IRQ Clear and Global IRQ Clear */
326	wmb();
327	writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
328}
329
330static void vfe_violation_read(struct vfe_device *vfe)
331{
332	u32 violation = readl_relaxed(vfe->base + VFE_VIOLATION_STATUS);
333
334	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);
335}
336
337/*
338 * vfe_isr - VFE module interrupt handler
339 * @irq: Interrupt line
340 * @dev: VFE device
341 *
342 * Return IRQ_HANDLED on success
343 */
344static irqreturn_t vfe_isr(int irq, void *dev)
345{
346	struct vfe_device *vfe = dev;
347	u32 status0, status1, vfe_bus_status[VFE_LINE_NUM_MAX];
348	int i, wm;
349
350	status0 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_0);
351	status1 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_1);
352
353	writel_relaxed(status0, vfe->base + VFE_IRQ_CLEAR_0);
354	writel_relaxed(status1, vfe->base + VFE_IRQ_CLEAR_1);
355
356	for (i = VFE_LINE_RDI0; i < vfe->line_num; i++) {
357		vfe_bus_status[i] = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(i));
358		writel_relaxed(vfe_bus_status[i], vfe->base + VFE_BUS_IRQ_CLEAR(i));
359	}
360
361	/* Enforce ordering between IRQ reading and interpretation */
362	wmb();
363
364	writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
365	writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
366
367	if (status0 & STATUS_0_RESET_ACK)
368		vfe->isr_ops.reset_ack(vfe);
369
370	for (i = VFE_LINE_RDI0; i < vfe->line_num; i++)
371		if (status0 & STATUS_0_RDI_REG_UPDATE(i))
372			vfe->isr_ops.reg_update(vfe, i);
373
374	for (i = VFE_LINE_RDI0; i < vfe->line_num; i++)
375		if (status0 & STATUS_1_RDI_SOF(i))
376			vfe->isr_ops.sof(vfe, i);
377
378	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)
379		if (vfe_bus_status[0] & STATUS0_COMP_BUF_DONE(i))
380			vfe->isr_ops.comp_done(vfe, i);
381
382	for (wm = 0; wm < MSM_VFE_IMAGE_MASTERS_NUM; wm++)
383		if (status0 & BIT(9))
384			if (vfe_bus_status[1] & STATUS1_WM_CLIENT_BUF_DONE(wm))
385				vfe->isr_ops.wm_done(vfe, wm);
386
387	return IRQ_HANDLED;
388}
389
390/*
391 * vfe_halt - Trigger halt on VFE module and wait to complete
392 * @vfe: VFE device
393 *
394 * Return 0 on success or a negative error code otherwise
395 */
396static int vfe_halt(struct vfe_device *vfe)
397{
398	/* rely on vfe_disable_output() to stop the VFE */
399	return 0;
400}
401
402static int vfe_get_output(struct vfe_line *line)
403{
404	struct vfe_device *vfe = to_vfe(line);
405	struct vfe_output *output;
406	unsigned long flags;
407	int wm_idx;
408
409	spin_lock_irqsave(&vfe->output_lock, flags);
410
411	output = &line->output;
412	if (output->state > VFE_OUTPUT_RESERVED) {
413		dev_err(vfe->camss->dev, "Output is running\n");
414		goto error;
415	}
416
417	output->wm_num = 1;
418
419	wm_idx = vfe_reserve_wm(vfe, line->id);
420	if (wm_idx < 0) {
421		dev_err(vfe->camss->dev, "Can not reserve wm\n");
422		goto error_get_wm;
423	}
424	output->wm_idx[0] = wm_idx;
425
426	output->drop_update_idx = 0;
427
428	spin_unlock_irqrestore(&vfe->output_lock, flags);
429
430	return 0;
431
432error_get_wm:
433	vfe_release_wm(vfe, output->wm_idx[0]);
434	output->state = VFE_OUTPUT_OFF;
435error:
436	spin_unlock_irqrestore(&vfe->output_lock, flags);
437
438	return -EINVAL;
439}
440
441static int vfe_enable_output(struct vfe_line *line)
442{
443	struct vfe_device *vfe = to_vfe(line);
444	struct vfe_output *output = &line->output;
445	const struct vfe_hw_ops *ops = vfe->ops;
446	struct media_entity *sensor;
447	unsigned long flags;
448	unsigned int frame_skip = 0;
449	unsigned int i;
450
451	sensor = camss_find_sensor(&line->subdev.entity);
452	if (sensor) {
453		struct v4l2_subdev *subdev = media_entity_to_v4l2_subdev(sensor);
454
455		v4l2_subdev_call(subdev, sensor, g_skip_frames, &frame_skip);
456		/* Max frame skip is 29 frames */
457		if (frame_skip > VFE_FRAME_DROP_VAL - 1)
458			frame_skip = VFE_FRAME_DROP_VAL - 1;
459	}
460
461	spin_lock_irqsave(&vfe->output_lock, flags);
462
463	ops->reg_update_clear(vfe, line->id);
464
465	if (output->state > VFE_OUTPUT_RESERVED) {
466		dev_err(vfe->camss->dev, "Output is not in reserved state %d\n",
467			output->state);
468		spin_unlock_irqrestore(&vfe->output_lock, flags);
469		return -EINVAL;
470	}
471
472	WARN_ON(output->gen2.active_num);
473
474	output->state = VFE_OUTPUT_ON;
475
476	output->sequence = 0;
477	output->wait_reg_update = 0;
478	reinit_completion(&output->reg_update);
479
480	vfe_wm_start(vfe, output->wm_idx[0], line);
481
482	for (i = 0; i < 2; i++) {
483		output->buf[i] = vfe_buf_get_pending(output);
484		if (!output->buf[i])
485			break;
486		output->gen2.active_num++;
487		vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line);
488	}
489
490	ops->reg_update(vfe, line->id);
491
492	spin_unlock_irqrestore(&vfe->output_lock, flags);
493
494	return 0;
495}
496
497/*
498 * vfe_enable - Enable streaming on VFE line
499 * @line: VFE line
500 *
501 * Return 0 on success or a negative error code otherwise
502 */
503static int vfe_enable(struct vfe_line *line)
504{
505	struct vfe_device *vfe = to_vfe(line);
506	int ret;
507
508	mutex_lock(&vfe->stream_lock);
509
510	if (!vfe->stream_count)
511		vfe_enable_irq_common(vfe);
512
513	vfe->stream_count++;
514
515	mutex_unlock(&vfe->stream_lock);
516
517	ret = vfe_get_output(line);
518	if (ret < 0)
519		goto error_get_output;
520
521	ret = vfe_enable_output(line);
522	if (ret < 0)
523		goto error_enable_output;
524
525	vfe->was_streaming = 1;
526
527	return 0;
528
529error_enable_output:
530	vfe_put_output(line);
531
532error_get_output:
533	mutex_lock(&vfe->stream_lock);
534
535	vfe->stream_count--;
536
537	mutex_unlock(&vfe->stream_lock);
538
539	return ret;
540}
541
542/*
543 * vfe_isr_sof - Process start of frame interrupt
544 * @vfe: VFE Device
545 * @line_id: VFE line
546 */
547static void vfe_isr_sof(struct vfe_device *vfe, enum vfe_line_id line_id)
548{
549	/* nop */
550}
551
552/*
553 * vfe_isr_reg_update - Process reg update interrupt
554 * @vfe: VFE Device
555 * @line_id: VFE line
556 */
557static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
558{
559	struct vfe_output *output;
560	unsigned long flags;
561
562	spin_lock_irqsave(&vfe->output_lock, flags);
563	vfe->ops->reg_update_clear(vfe, line_id);
564
565	output = &vfe->line[line_id].output;
566
567	if (output->wait_reg_update) {
568		output->wait_reg_update = 0;
569		complete(&output->reg_update);
570	}
571
572	spin_unlock_irqrestore(&vfe->output_lock, flags);
573}
574
575/*
576 * vfe_isr_wm_done - Process write master done interrupt
577 * @vfe: VFE Device
578 * @wm: Write master id
579 */
580static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm)
581{
582	struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]];
583	struct camss_buffer *ready_buf;
584	struct vfe_output *output;
585	unsigned long flags;
586	u32 index;
587	u64 ts = ktime_get_ns();
588
589	spin_lock_irqsave(&vfe->output_lock, flags);
590
591	if (vfe->wm_output_map[wm] == VFE_LINE_NONE) {
592		dev_err_ratelimited(vfe->camss->dev,
593				    "Received wm done for unmapped index\n");
594		goto out_unlock;
595	}
596	output = &vfe->line[vfe->wm_output_map[wm]].output;
597
598	ready_buf = output->buf[0];
599	if (!ready_buf) {
600		dev_err_ratelimited(vfe->camss->dev,
601				    "Missing ready buf %d!\n", output->state);
602		goto out_unlock;
603	}
604
605	ready_buf->vb.vb2_buf.timestamp = ts;
606	ready_buf->vb.sequence = output->sequence++;
607
608	index = 0;
609	output->buf[0] = output->buf[1];
610	if (output->buf[0])
611		index = 1;
612
613	output->buf[index] = vfe_buf_get_pending(output);
614
615	if (output->buf[index])
616		vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line);
617	else
618		output->gen2.active_num--;
619
620	spin_unlock_irqrestore(&vfe->output_lock, flags);
621
622	vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
623
624	return;
625
626out_unlock:
627	spin_unlock_irqrestore(&vfe->output_lock, flags);
628}
629
630/*
631 * vfe_queue_buffer - Add empty buffer
632 * @vid: Video device structure
633 * @buf: Buffer to be enqueued
634 *
635 * Add an empty buffer - depending on the current number of buffers it will be
636 * put in pending buffer queue or directly given to the hardware to be filled.
637 *
638 * Return 0 on success or a negative error code otherwise
639 */
640static int vfe_queue_buffer(struct camss_video *vid,
641			    struct camss_buffer *buf)
642{
643	struct vfe_line *line = container_of(vid, struct vfe_line, video_out);
644	struct vfe_device *vfe = to_vfe(line);
645	struct vfe_output *output;
646	unsigned long flags;
647
648	output = &line->output;
649
650	spin_lock_irqsave(&vfe->output_lock, flags);
651
652	if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) {
653		output->buf[output->gen2.active_num++] = buf;
654		vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line);
655	} else {
656		vfe_buf_add_pending(output, buf);
657	}
658
659	spin_unlock_irqrestore(&vfe->output_lock, flags);
660
661	return 0;
662}
663
664static const struct vfe_isr_ops vfe_isr_ops_170 = {
665	.reset_ack = vfe_isr_reset_ack,
666	.halt_ack = vfe_isr_halt_ack,
667	.reg_update = vfe_isr_reg_update,
668	.sof = vfe_isr_sof,
669	.comp_done = vfe_isr_comp_done,
670	.wm_done = vfe_isr_wm_done,
671};
672
673static const struct camss_video_ops vfe_video_ops_170 = {
674	.queue_buffer = vfe_queue_buffer,
675	.flush_buffers = vfe_flush_buffers,
676};
677
678static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
679{
680	vfe->isr_ops = vfe_isr_ops_170;
681	vfe->video_ops = vfe_video_ops_170;
682}
683
684const struct vfe_hw_ops vfe_ops_170 = {
685	.global_reset = vfe_global_reset,
686	.hw_version = vfe_hw_version,
687	.isr_read = vfe_isr_read,
688	.isr = vfe_isr,
689	.pm_domain_off = vfe_pm_domain_off,
690	.pm_domain_on = vfe_pm_domain_on,
691	.reg_update_clear = vfe_reg_update_clear,
692	.reg_update = vfe_reg_update,
693	.subdev_init = vfe_subdev_init,
694	.vfe_disable = vfe_disable,
695	.vfe_enable = vfe_enable,
696	.vfe_halt = vfe_halt,
697	.violation_read = vfe_violation_read,
698	.vfe_wm_stop = vfe_wm_stop,
699};
700