Searched refs:writel_relaxed (Results 226 - 250 of 698) sorted by relevance

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/linux-master/drivers/spi/
H A Dspi-bcm-qspi.h77 writel_relaxed(data, addr);
/linux-master/arch/arm/include/asm/
H A Darch_gicv3.h146 writel_relaxed((u32)val, addr);
147 writel_relaxed((u32)(val >> 32), addr + 4);
191 #define gic_write_lpir(v, c) writel_relaxed(lower_32_bits(v), c)
226 writel_relaxed(tmp, addr + 4);
/linux-master/drivers/clk/berlin/
H A Dberlin2-div.c94 writel_relaxed(reg, div->base + map->gate_offs);
113 writel_relaxed(reg, div->base + map->gate_offs);
134 writel_relaxed(reg, div->base + map->pll_switch_offs);
141 writel_relaxed(reg, div->base + map->pll_select_offs);
/linux-master/drivers/gpu/drm/armada/
H A Darmada_drm.h28 writel_relaxed(v, ptr);
/linux-master/drivers/phy/marvell/
H A Dphy-mmp3-hsic.c25 writel_relaxed(hsic_ctrl, base + HSIC_CTRL);
/linux-master/drivers/mailbox/
H A Dmailbox-mpfs.c124 writel_relaxed(word_buf[index],
138 writel_relaxed(val, mbox->mbox_base + msg->mbox_offset + index * 0x4);
146 writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET);
188 writel_relaxed(0, mbox->int_reg);
H A Dhi3660-mailbox.c189 writel_relaxed(~BIT(mchan->dst_irq), base + MBOX_IMASK_REG);
192 writel_relaxed(BIT(mchan->dst_irq), base + MBOX_DST_REG);
195 writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG);
199 writel_relaxed(buf[i], base + MBOX_DATA_REG + i * 4);
/linux-master/drivers/watchdog/
H A Dst_lpc_wdt.c84 writel_relaxed(timeout * clkrate, st_wdog->base + LPC_LPA_LSB_OFF);
85 writel_relaxed(1, st_wdog->base + LPC_LPA_START_OFF);
92 writel_relaxed(1, st_wdog->base + LPC_WDT_OFF);
101 writel_relaxed(0, st_wdog->base + LPC_WDT_OFF);
/linux-master/drivers/char/hw_random/
H A Dexynos-trng.c65 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL);
94 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
98 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);
104 writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL);
/linux-master/drivers/regulator/
H A Dstm32-vrefbuf.c53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
67 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
88 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
126 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
/linux-master/drivers/net/dsa/
H A Dbcm_sf2.h140 writel_relaxed(val, priv->name + off); \
190 writel_relaxed(val, priv->core + tmp);
200 writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
219 writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
/linux-master/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7110.c285 writel_relaxed(dout, reg_dout);
287 writel_relaxed(doen, reg_doen);
290 writel_relaxed(ival, reg_din);
371 writel_relaxed(value, reg);
628 writel_relaxed(dout, reg_dout);
703 writel_relaxed(value, ic);
704 writel_relaxed(value | mask, ic);
721 writel_relaxed(value, ie);
742 writel_relaxed(value, ie);
745 writel_relaxed(valu
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/linux-master/drivers/hwtracing/coresight/
H A Dcoresight-etb10.c112 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
115 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
118 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
120 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
122 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
123 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
126 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
261 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
264 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
272 writel_relaxed(
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H A Dcoresight-replicator.c55 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0);
56 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1);
110 writel_relaxed(id0val, drvdata->base + REPLICATOR_IDFILTER0);
111 writel_relaxed(id1val, drvdata->base + REPLICATOR_IDFILTER1);
166 writel_relaxed(0xff, drvdata->base + reg);
/linux-master/drivers/clocksource/
H A Dtimer-microchip-pit64b.c127 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
128 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
129 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
130 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
131 writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
132 writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
137 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
/linux-master/drivers/irqchip/
H A Dirq-mmp.c79 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
87 writel_relaxed(r, data->reg_mask);
103 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
112 writel_relaxed(r, mmp_icu2_base + (hwirq << 2));
116 writel_relaxed(r, data->reg_mask);
132 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
135 writel_relaxed(r, data->reg_mask);
H A Dirq-imx-intmux.c94 writel_relaxed(val, reg);
113 writel_relaxed(val, reg);
268 writel_relaxed(0, data->regs + CHANIER(i));
296 writel_relaxed(0, data->regs + CHANIER(i));
338 writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i));
H A Dirq-imx-irqsteer.c57 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
71 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
195 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
262 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
264 writel_relaxed(data->saved_reg[i],
/linux-master/drivers/mtd/nand/raw/
H A Drenesas-nand-controller.c265 writel_relaxed(control, rnandc->regs + CONTROL_REG);
274 writel_relaxed(control, rnandc->regs + CONTROL_REG);
279 writel_relaxed(0, rnandc->regs + INT_STATUS_REG);
280 writel_relaxed(0, rnandc->regs + ECC_STAT_REG);
281 writel_relaxed(0, rnandc->regs + ECC_CNT_REG);
286 writel_relaxed(0, rnandc->regs + INT_MASK_REG);
292 writel_relaxed(val, rnandc->regs + INT_MASK_REG);
297 writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG);
310 writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG);
311 writel_relaxed(rnan
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/linux-master/drivers/dma/
H A Dmilbeaut-xdmac.c119 writel_relaxed(val, mc->reg_ch_base + M10V_XDTBC);
122 writel_relaxed(val, mc->reg_ch_base + M10V_XDSSA);
125 writel_relaxed(val, mc->reg_ch_base + M10V_XDDSA);
131 writel_relaxed(val, mc->reg_ch_base + M10V_XDSAC);
137 writel_relaxed(val, mc->reg_ch_base + M10V_XDDAC);
146 writel_relaxed(val, mc->reg_ch_base + M10V_XDDES);
169 writel_relaxed(val, mc->reg_ch_base + M10V_XDDSD);
/linux-master/drivers/gpu/drm/meson/
H A Dmeson_encoder_hdmi.c234 writel_relaxed(2 | (2 << 2),
238 writel_relaxed(1 | (2 << 2),
242 writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
247 writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
249 writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
261 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
262 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
/linux-master/arch/arm64/kvm/vgic/
H A Dvgic-v2.c18 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
420 writel_relaxed(0, base + GICH_LR0 + (i * 4));
434 writel_relaxed(0, base + GICH_HCR);
449 writel_relaxed(cpu_if->vgic_hcr, base + GICH_HCR);
451 writel_relaxed(cpu_if->vgic_lr[i],
461 writel_relaxed(cpu_if->vgic_vmcr,
463 writel_relaxed(cpu_if->vgic_apr,
/linux-master/drivers/soc/ti/
H A Dknav_qmss_acc.c73 writel_relaxed(mask, pdsp->intd + offset);
113 writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
115 writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
186 writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
189 writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
286 writel_relaxed(cmd->timer_config, &pdsp->acc_command->timer_config);
287 writel_relaxed(cmd->queue_num, &pdsp->acc_command->queue_num);
288 writel_relaxed(cmd->list_dma, &pdsp->acc_command->list_dma);
289 writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask);
290 writel_relaxed(cm
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/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c215 writel_relaxed(reg_ctl[0], pll->ctl0_base);
216 writel_relaxed(reg_ctl[1], pll->ctl1_base);
217 writel_relaxed(reg_ctl[2], pll->ctl2_base);
294 writel_relaxed(val, pll->ctl1_base);
305 writel_relaxed(val, pll->ctl1_base);
/linux-master/drivers/clk/tegra/
H A Dclk.c114 writel_relaxed(BIT(id % 32),
128 writel_relaxed(BIT(id % 32),
174 writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
197 writel_relaxed(periph_state_ctx[idx],
207 writel_relaxed(periph_state_ctx[idx],

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