Searched refs:writel_relaxed (Results 151 - 175 of 698) sorted by relevance

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/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A Dpll.c257 writel_relaxed(l, base + PLL_CONFIGURATION1);
266 writel_relaxed(l, base + PLL_CONFIGURATION3);
291 writel_relaxed(l, base + PLL_CONFIGURATION2);
293 writel_relaxed(1, base + PLL_GO); /* PLL_GO */
314 writel_relaxed(l, base + PLL_CONFIGURATION2);
340 writel_relaxed(l, base + PLL_CONFIGURATION1);
354 writel_relaxed(l, base + PLL_CONFIGURATION2);
358 writel_relaxed(l, base + PLL_CONFIGURATION3);
363 writel_relaxed(l, base + PLL_CONFIGURATION4);
365 writel_relaxed(
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/linux-master/drivers/clk/imx/
H A Dclk-pllv3.c83 writel_relaxed(val, pll->base);
98 writel_relaxed(val, pll->base);
145 writel_relaxed(val, pll->base);
200 writel_relaxed(val, pll->base);
287 writel_relaxed(val, pll->base);
288 writel_relaxed(mfn, pll->base + pll->num_offset);
289 writel_relaxed(mfd, pll->base + pll->denom_offset);
379 writel_relaxed(val, pll->base);
381 writel_relaxed(mf.mfn, pll->base + pll->num_offset);
382 writel_relaxed(m
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/linux-master/drivers/mmc/host/
H A Dsdhci-st.c128 writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
129 writel_relaxed(ST_TOP_MMC_DLY_MAX,
156 writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
176 writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
182 writel_relaxed(ST_MMC_GP_OUTPUT_CD,
209 writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
210 writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
211 writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
219 writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF, ioaddr + ST_TOP_MMC_DLY_CTRL);
220 writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALI
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H A Dsdhci-msm.c328 writel_relaxed(val, msm_host->core_mem + offset);
334 writel_relaxed(val, host->ioaddr + offset);
442 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
456 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
460 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
470 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
620 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
647 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
650 writel_relaxed(msm_host->dll_config,
657 writel_relaxed(confi
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H A Dmmci_stm32_sdmmc.c239 writel_relaxed(dma_addr,
241 writel_relaxed(MMCI_STM32_IDMAEN,
258 writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
259 writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
260 writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
261 writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
262 writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
276 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
290 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
356 writel_relaxed(
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/linux-master/drivers/thermal/st/
H A Dstm_thermal.c117 writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
134 writel_relaxed(ICIFR_MASK, sensor->base + DTS_ICIFR_OFFSET);
147 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
164 writel_relaxed(value, sensor->base +
181 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
189 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
235 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
297 writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
344 writel_relaxed(itr1, sensor->base + DTS_ITR1_OFFSET);
522 writel_relaxed(ICIFR_MAS
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/linux-master/drivers/crypto/stm32/
H A Dstm32-crc32.c131 writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
132 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
133 writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
176 writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
177 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
178 writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
183 writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
190 writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
195 writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
199 writel_relaxed(CRC_CR_REV_IN_BYT
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/linux-master/drivers/media/rc/
H A Dir-hix5hd2.c126 writel_relaxed(val, priv->base + IR_ENABLE);
153 writel_relaxed(val, priv->base + IR_CONFIG);
155 writel_relaxed(0x00, priv->base + IR_INTM);
157 writel_relaxed(0x01, priv->base + IR_START);
204 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
233 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
235 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
379 writel_relaxed(0x00, priv->base + IR_INTM);
380 writel_relaxed(0xff, priv->base + IR_INTC);
381 writel_relaxed(
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/linux-master/drivers/memory/tegra/
H A Dtegra30-emc.c403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL);
432 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
469 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2);
480 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3);
491 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL);
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG);
620 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
639 writel_relaxed(timing->data[i],
662 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT);
685 writel_relaxed(
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/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss-ispif.c174 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
175 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
177 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
178 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
179 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
239 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
240 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
300 writel_relaxed(va
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/linux-master/sound/soc/apple/
H A Dmca.c173 writel_relaxed(newval, ptr);
287 writel_relaxed(cl->no + 1, cl->base + REG_SYNCGEN_MCLK_SEL);
441 writel_relaxed(0xffffffff,
443 writel_relaxed(~((u32)mca_crop_mask(mask, nchans)),
445 writel_relaxed(0xffffffff,
447 writel_relaxed(~((u32)mask),
450 writel_relaxed(0xffffffff,
452 writel_relaxed(~((u32)mca_crop_mask(mask, nchans)),
454 writel_relaxed(1 << port,
526 writel_relaxed(bitstar
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/linux-master/drivers/spi/
H A Dspi-stm32-qspi.c140 writel_relaxed(cr, qspi->io_base + QSPI_CR);
149 writel_relaxed(cr, qspi->io_base + QSPI_CR);
259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
270 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
313 writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
326 writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
339 writel_relaxed(cr | CR_SMIE, qspi->io_base + QSPI_CR);
345 writel_relaxed(FCR_CSMF, qspi->io_base + QSPI_FCR);
374 writel_relaxed(cr, qspi->io_base + QSPI_CR);
377 writel_relaxed(o
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H A Dspi-axi-spi-engine.c355 writel_relaxed(buf[i], addr);
378 writel_relaxed(buf[i], addr);
386 writel_relaxed(buf[i], addr);
394 writel_relaxed(buf[i], addr);
460 writel_relaxed(SPI_ENGINE_INT_SYNC,
494 writel_relaxed(spi_engine->int_enable,
565 writel_relaxed(int_enable,
586 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
587 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
588 writel_relaxed(
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/linux-master/drivers/mailbox/
H A Dmailbox-altera.c85 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG);
97 writel_relaxed(mask, mbox->mbox_base + MAILBOX_INTMASK_REG);
107 writel_relaxed(MBOX_MAGIC, mbox->mbox_base + MAILBOX_PTR_REG);
111 writel_relaxed(0, mbox->mbox_base + MAILBOX_PTR_REG);
227 writel_relaxed(udata[MBOX_PTR], mbox->mbox_base + MAILBOX_PTR_REG);
228 writel_relaxed(udata[MBOX_CMD], mbox->mbox_base + MAILBOX_CMD_REG);
270 writel_relaxed(~0, mbox->mbox_base + MAILBOX_INTMASK_REG);
/linux-master/drivers/watchdog/
H A Domap_wdt.c80 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
93 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
97 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
107 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
111 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
126 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
153 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
/linux-master/arch/arm/mm/
H A Dcache-uniphier.c100 writel_relaxed(UNIPHIER_SSCOPE_CM_SYNC,
147 writel_relaxed(UNIPHIER_SSCOLPQS_EF, data->op_base + UNIPHIER_SSCOLPQS);
151 writel_relaxed(UNIPHIER_SSCOQM_CE | operation,
156 writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD);
157 writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ);
226 writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC);
235 writel_relaxed(data->way_mask, data->way_ctrl_base + 4 * cpu);
H A Dcache-l2x0.c72 writel_relaxed(val, base + reg);
87 writel_relaxed(l2x0_way_mask, reg);
96 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
98 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
125 writel_relaxed(0, base + sync_reg_offset);
175 writel_relaxed(0, base + sync_reg_offset);
182 writel_relaxed(start, reg);
193 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
199 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
270 writel_relaxed(
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/linux-master/drivers/dma/
H A Dapple-admac.c209 writel_relaxed((curr & ~mask) | (val & mask), addr);
298 writel_relaxed(lower_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
299 writel_relaxed(upper_32_bits(addr), ad->base + REG_DESC_WRITE(channo));
300 writel_relaxed(tx->period_len, ad->base + REG_DESC_WRITE(channo));
301 writel_relaxed(FLAG_DESC_NOTIFY, ad->base + REG_DESC_WRITE(channo));
414 writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
416 writel_relaxed(STATUS_DESC_DONE | STATUS_ERR,
421 writel_relaxed(startbit, ad->base + REG_TX_START);
424 writel_relaxed(startbit, ad->base + REG_RX_START);
439 writel_relaxed(stopbi
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/linux-master/drivers/irqchip/
H A Dirq-renesas-rzg2l.c102 writel_relaxed(iscr & ~bit, priv->base + ISCR);
118 writel_relaxed(reg & ~bit, priv->base + TSCR);
158 writel_relaxed(reg, priv->base + TSSR(tssr_index));
213 writel_relaxed(tmp, priv->base + IITSR);
229 writel_relaxed(reg, priv->base + TSSR(tssr_index));
269 writel_relaxed(reg, priv->base + TITSR(index));
271 writel_relaxed(tssr, priv->base + TSSR(tssr_index));
315 writel_relaxed(cache->titsr[i], base + TITSR(i));
316 writel_relaxed(cache->iitsr, base + IITSR);
H A Dexynos-combiner.c55 writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
62 writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
133 writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
231 writel_relaxed(combiner_data[i].irq_mask,
233 writel_relaxed(combiner_data[i].pm_save,
H A Dirq-mtk-cirq.c87 writel_relaxed(mask, mtk_cirq_irq_reg(chip_data, idx, cirq_num));
247 writel_relaxed(mask, reg);
255 writel_relaxed(value, reg);
267 writel_relaxed(value | CIRQ_FLUSH, reg);
272 writel_relaxed(value, reg);
H A Dirq-mchp-eic.c53 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
64 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
96 writel_relaxed(tmp, eic->base + MCHP_EIC_SCFG(d->hwirq));
134 writel_relaxed(eic->scfg[hwirq], eic->base +
237 writel_relaxed(0UL, eic->base + MCHP_EIC_SCFG(i));
/linux-master/drivers/media/platform/st/sti/hva/
H A Dhva-hw.c110 writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
214 writel_relaxed(0x1, hva->regs + HVA_HIF_REG_IT_ACK);
489 writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
495 writel_relaxed(BSM_CFG_VAL1, hva->regs + HVA_HIF_REG_BSM);
498 writel_relaxed(MIF_CFG_VAL3, hva->regs + HVA_HIF_REG_MIF_CFG);
499 writel_relaxed(HEC_MIF_CFG_VAL, hva->regs + HVA_HIF_REG_HEC_MIF_CFG);
509 writel_relaxed(cmd + (client_id << 8), hva->regs + HVA_HIF_FIFO_CMD);
510 writel_relaxed(task->paddr, hva->regs + HVA_HIF_FIFO_CMD);
533 writel_relaxed(reg, hva->regs + HVA_HIF_REG_CLK_GATING);
/linux-master/drivers/clocksource/
H A Dtimer-rockchip.c57 writel_relaxed(TIMER_DISABLE, timer->ctrl);
62 writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
68 writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
69 writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
74 writel_relaxed(1, timer->base + TIMER_INT_STATUS);
/linux-master/drivers/staging/media/rkvdec/
H A Drkvdec-h264.c908 writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
927 writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
931 writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
932 writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_RLCWRITE_BASE);
936 writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
940 writel_relaxed(priv_start_addr + offset,
945 writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
948 writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
951 writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
975 writel_relaxed(dp
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