Searched refs:reg_val (Results 226 - 250 of 396) sorted by relevance

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/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_prototype.h86 u32 reg_addr, u64 reg_val,
89 u32 reg_addr, u64 *reg_val,
427 u32 reg_addr, u32 *reg_val,
431 u32 reg_addr, u32 reg_val,
433 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
438 u32 reg_addr, u32 reg_val,
444 u32 reg_addr, u32 *reg_val,
/linux-master/drivers/ntb/hw/amd/
H A Dntb_hw_amd.c126 u64 base_addr, limit, reg_val; local
156 reg_val = read64(peer_mmio + xlat_reg);
157 if (reg_val != addr) {
164 reg_val = read64(peer_mmio + limit_reg);
165 if (reg_val != limit) {
179 reg_val = read64(peer_mmio + xlat_reg);
180 if (reg_val != addr) {
187 reg_val = readl(peer_mmio + limit_reg);
188 if (reg_val != limit) {
974 dev_dbg(&ndev->ntb.pdev->dev, "%s: reg_val
[all...]
/linux-master/drivers/pinctrl/
H A Dpinctrl-cy8c95x0.c799 u32 reg_val; local
802 ret = cy8c95x0_regmap_read(chip, CY8C95X0_INPUT, port, &reg_val);
813 return !!(reg_val & bit);
831 u32 reg_val; local
834 ret = cy8c95x0_regmap_read(chip, CY8C95X0_DIRECTION, port, &reg_val);
838 if (reg_val & bit)
854 u32 reg_val; local
912 ret = cy8c95x0_regmap_read(chip, reg, port, &reg_val);
916 if (reg_val & bit)
/linux-master/drivers/pmdomain/imx/
H A Dgpcv2.c319 u32 reg_val, pgc; local
359 domain->regs->pup, reg_val,
360 !(reg_val & domain->bits.pxx),
385 * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
386 * (reg_val & domain->bits.hskack), 0,
405 regmap_read_bypassed(domain->regmap, domain->regs->hsk, &reg_val);
429 u32 reg_val, pgc; local
447 reg_val,
448 !(reg_val & domain->bits.hskack),
471 domain->regs->pdn, reg_val,
[all...]
/linux-master/drivers/gpu/drm/i915/
H A Dintel_uncore.h491 u32 reg_val; local
494 reg_val = intel_uncore_read(uncore, reg);
496 return (reg_val & mask) != expected_val ? -EINVAL : 0;
H A Di915_hwmon.c133 u32 reg_val; local
143 reg_val = intel_uncore_read(uncore, rgaddr);
145 if (reg_val >= ei->reg_val_prev)
146 ei->accum_energy += reg_val - ei->reg_val_prev;
148 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
149 ei->reg_val_prev = reg_val;
/linux-master/drivers/iio/light/
H A Dltrf216a.c159 u8 reg_val; local
169 reg_val = ltrf216a_int_time_reg[i][1];
171 ret = regmap_write(data->regmap, LTRF216A_ALS_MEAS_RES, reg_val);
/linux-master/drivers/perf/
H A Dmarvell_cn10k_tad_pmu.c85 u64 reg_val; local
99 reg_val = event_idx & 0xFF;
100 writeq_relaxed(reg_val, tad_pmu->regions[i].base +
/linux-master/drivers/net/dsa/microchip/
H A Dksz8795.c737 u8 reg_val; local
742 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], &reg_val);
746 if (reg_val & PORT_MDIX_STATUS)
749 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, &reg_val);
753 if (reg_val & PORT_FORCE_LINK)
756 if (reg_val & PORT_POWER_SAVING)
759 if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
995 u8 reg_val = 0; local
999 reg_val |= PORT_FORCE_LINK;
1002 reg_val |
[all...]
/linux-master/include/ufs/
H A Dufshci.h367 __le32 reg_val; member in union:ufs_crypto_capabilities
393 __le32 reg_val; member in union:ufs_crypto_cap_entry
406 __le32 reg_val[32]; member in union:ufs_crypto_cfg_entry
/linux-master/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c3242 u32 reg_base, reg_val; local
3266 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 1);
3267 WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);
3276 reg_val = FIELD_PREP(ARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN_VAL_MASK, 0);
3277 WREG32(reg_base + ARC_DCCM_UPPER_EN_OFFSET, reg_val);
4009 u32 reg_val; local
4011 reg_val = FIELD_PREP(PDMA0_CORE_CFG_1_HALT_MASK, 0x1);
4012 WREG32(reg_base + DMA_CORE_CFG_1_OFFSET, reg_val);
4080 u32 reg_val; local
4086 reg_val
4497 u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1); local
4537 u32 reg_val = FIELD_PREP(DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK, 0x1); local
4591 u32 reg_base, reg_val; local
4700 u32 reg_base, reg_addr, reg_val, tpc_id; local
4727 u32 reg_base, reg_addr, reg_val, mme_id; local
4745 u32 reg_base, reg_addr, reg_val, edma_id; local
5404 u32 reg_val; local
5446 u32 reg_val; local
6320 u32 reg_val; local
6385 u32 reg_val; local
7621 u32 vdec_id, i, ports_offset, reg_val; local
7716 u32 reg_base, reg_offset, reg_val = 0; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h115 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,
/linux-master/drivers/gpio/
H A Dgpio-aspeed-sgpio.c87 reg_val, enumerator in enum:aspeed_sgpio_reg
109 case reg_val:
179 reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
200 addr_w = bank_reg(gpio, bank, reg_val);
/linux-master/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_regs.c180 u32 *reg_val = data; local
215 *reg_val++ = le32_to_cpu(*desc_data++);
234 u64 *reg_val = data; local
269 *reg_val++ = le64_to_cpu(*desc_data++);
H A Dhclge_mdio.c290 return le16_to_cpu(req->reg_val);
303 req->reg_val = cpu_to_le16(val);
/linux-master/drivers/media/dvb-frontends/
H A Daf9033_priv.h19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_3
[all...]
/linux-master/sound/soc/tegra/
H A Dtegra210_ahub.c30 unsigned int reg_val; local
33 reg_val = snd_soc_component_read(cmpnt, reg);
34 reg_val &= ahub->soc_data->mask[i];
36 if (reg_val) {
37 bit_pos = ffs(reg_val) +
64 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; local
74 reg_val = BIT(bit_pos);
84 update[i].val = (i == reg_idx) ? reg_val : 0;
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_common.h79 int prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
80 int prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
/linux-master/drivers/bluetooth/
H A Dbtrtl.c526 u8 reg_val[2]; local
541 rc = btrtl_vendor_read_reg16(hdev, RTL_SEC_PROJ, reg_val);
544 key_id = reg_val[0];
1061 u8 reg_val[2]; local
1072 ret = btrtl_vendor_read_reg16(hdev, RTL_CHIP_SUBVER, reg_val);
1075 lmp_subver = get_unaligned_le16(reg_val);
1078 ret = btrtl_vendor_read_reg16(hdev, RTL_CHIP_REV, reg_val);
1081 hci_rev = get_unaligned_le16(reg_val);
/linux-master/drivers/remoteproc/
H A Dpru_rproc.c439 u32 reg_val; local
445 reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL);
448 pru->dbg_continuous = reg_val;
451 reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN;
453 reg_val = pru->dbg_continuous;
456 pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val);
/linux-master/drivers/thermal/ti-soc-thermal/
H A Dti-bandgap.c361 int reg_val; local
365 reg_val = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl);
366 reg_val = (reg_val & tsr->mask_counter_delay_mask) >>
368 switch (reg_val) {
389 reg_val);
/linux-master/drivers/memory/
H A Dmtk-smi.c197 u32 sec_con_val, reg_val; local
211 reg_val = readl(common->smi_ao_base
213 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
214 reg_val |= sec_con_val;
215 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
216 writel(reg_val,
/linux-master/sound/soc/codecs/
H A Drt5682.c2223 unsigned int reg_val = 0, tdm_ctrl = 0; local
2240 reg_val |= RT5682_I2S_BP_INV;
2264 reg_val |= RT5682_I2S_DF_LEFT;
2268 reg_val |= RT5682_I2S_DF_PCM_A;
2272 reg_val |= RT5682_I2S_DF_PCM_B;
2282 RT5682_I2S_DF_MASK, reg_val);
2291 reg_val |= RT5682_I2S2_MS_S;
2294 RT5682_I2S_DF_MASK, reg_val);
2307 unsigned int reg_val = 0, src = 0; local
2314 reg_val |
[all...]
H A Drt5640.c1772 unsigned int reg_val = 0; local
1780 reg_val |= RT5640_I2S_MS_S;
1791 reg_val |= RT5640_I2S_BP_INV;
1801 reg_val |= RT5640_I2S_DF_LEFT;
1804 reg_val |= RT5640_I2S_DF_PCM_A;
1807 reg_val |= RT5640_I2S_DF_PCM_B;
1821 RT5640_I2S_DF_MASK, reg_val);
1826 RT5640_I2S_DF_MASK, reg_val);
1837 unsigned int reg_val = 0; local
1847 reg_val |
[all...]
/linux-master/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.c849 u64 base, limit, reg_val; local
893 reg_val = ioread64(mmio + xlat_reg);
894 if (reg_val != addr) {
901 reg_val = ioread64(mmio + limit_reg);
902 if (reg_val != limit) {
924 reg_val = ioread32(mmio + xlat_reg);
925 if (reg_val != addr) {
932 reg_val = ioread32(mmio + limit_reg);
933 if (reg_val != limit) {
1220 u16 reg_val; local
[all...]

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