Searched refs:readl (Results 276 - 300 of 2405) sorted by relevance

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/linux-master/drivers/cxl/core/
H A Dregs.c52 cap_array = readl(base + CXL_CM_CAP_HDR_OFFSET);
69 hdr = readl(base + cap * 0x4);
74 hdr = readl(register_block);
140 readl(base + cap * 0x10));
141 offset = readl(base + cap * 0x10 + 0x4);
142 length = readl(base + cap * 0x10 + 0x8);
489 cap_hdr = readl(addr + offset);
496 cap_hdr = readl(addr + offset);
537 id = readl(addr + PCI_VENDOR_ID);
539 bar0 = readl(add
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/linux-master/drivers/clk/mvebu/
H A Dmv98dx3236.c73 cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
120 u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
H A Dkirkwood.c88 u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
110 u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
132 u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
139 u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
157 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
179 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
/linux-master/arch/m68k/coldfire/
H A Dintc-525x.c23 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
36 u32 imr = readl(MCFSIM2_GPIOINTENABLE);
H A Dm5272.c59 v = readl(MCFSIM_PBCNT);
63 v = readl(MCFSIM_PDCNT);
/linux-master/drivers/net/ethernet/brocade/bna/
H A Dbna_hw_defs.h157 init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
160 init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
165 (_cur_mask) = readl((_bna)->regs.fn_int_mask); \
174 mask = readl((bna)->regs.fn_int_mask); \
177 mask = readl((bna)->regs.fn_int_mask); \
183 mask = readl((bna)->regs.fn_int_mask); \
186 mask = readl((bna)->regs.fn_int_mask); \
191 (_status) = readl((_bna)->regs.fn_int_status); \
/linux-master/drivers/soc/bcm/brcmstb/
H A Dcommon.c62 family_id = readl(sun_top_ctrl_base);
63 product_id = readl(sun_top_ctrl_base + 0x4);
/linux-master/drivers/clk/
H A Dclk-moxart.c34 mul = readl(base + 0x30) >> 3 & 0x3f;
74 val = readl(base + 0xc) >> 4 & 0x7;
/linux-master/drivers/mmc/host/
H A Dtifm_sd.c126 val = readl(sock->addr + SOCK_MMCSD_DATA);
387 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
388 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
389 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
390 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
391 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
392 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
393 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
394 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
428 | readl(soc
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/linux-master/drivers/ptp/
H A Dptp_dfl_tod.c107 nanosec = readl(base + TOD_NANOSEC);
108 seconds_lsb = readl(base + TOD_SECONDSL);
109 seconds_msb = readl(base + TOD_SECONDSH);
135 rate = readl(base + TOD_CLK_FREQ);
193 period = readl(base + TOD_PERIOD);
237 nanosec = readl(base + TOD_NANOSEC);
238 seconds_lsb = readl(base + TOD_SECONDSL);
239 seconds_msb = readl(base + TOD_SECONDSH);
/linux-master/arch/arm/mach-berlin/
H A Dplatsmp.c37 val = readl(cpu_ctrl + CPU_RESET_NON_SC);
111 val = readl(cpu_ctrl + CPU_RESET_NON_SC);
/linux-master/arch/arm/mach-socfpga/
H A Dsocfpga.c72 temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
85 temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
/linux-master/drivers/phy/marvell/
H A Dphy-mvebu-cp110-utmi.c121 reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG);
128 reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG);
134 reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
140 reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
149 reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
158 reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
218 reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
233 reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
/linux-master/drivers/usb/host/
H A Dxhci-ext-caps.h133 val = readl(base + XHCI_HCC_PARAMS_OFFSET);
141 val = readl(base + offset);
/linux-master/drivers/rtc/
H A Drtc-mv.c73 rtc_time = readl(ioaddr + RTC_TIME_REG_OFFS);
74 rtc_date = readl(ioaddr + RTC_DATE_REG_OFFS);
104 rtc_time = readl(ioaddr + RTC_ALARM_TIME_REG_OFFS);
105 rtc_date = readl(ioaddr + RTC_ALARM_DATE_REG_OFFS);
125 alm->enabled = !!readl(ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS);
191 if (!readl(ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS))
228 rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS);
238 rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS);
/linux-master/drivers/scsi/csiostor/
H A Dcsio_defs.h56 return readl(addr) + ((u64)readl(addr + 4) << 32);
/linux-master/drivers/edac/
H A Dzynqmp_edac.c137 p->ceinfo.fault_lo = readl(base + CE_FFD0_OFST);
138 p->ceinfo.fault_hi = readl(base + CE_FFD1_OFST);
139 p->ceinfo.addr = (OCM_BASEVAL | readl(base + CE_FFA_OFST));
143 p->ueinfo.fault_lo = readl(base + UE_FFD0_OFST);
144 p->ueinfo.fault_hi = readl(base + UE_FFD1_OFST);
145 p->ueinfo.addr = (OCM_BASEVAL | readl(base + UE_FFA_OFST));
194 regval = readl(priv->baseaddr + OCM_ISR_OFST);
219 return readl(base + ECC_CTRL_OFST) & OCM_ECC_ENABLE_MASK;
/linux-master/drivers/video/fbdev/savage/
H A Dsavagefb-i2c.c50 r = readl(chan->ioaddr + chan->reg);
56 readl(chan->ioaddr + chan->reg); /* flush posted write */
64 r = readl(chan->ioaddr + chan->reg);
70 readl(chan->ioaddr + chan->reg); /* flush posted write */
77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN));
84 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SDA_IN));
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_tmds_clk.c131 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
135 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
154 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
160 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
173 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
186 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
/linux-master/drivers/clk/keystone/
H A Dgate.c77 mdctl = readl(control_base + MDCTL);
85 pdstat = readl(domain_base + PDSTAT);
87 pdctl = readl(domain_base + PDCTL);
95 ptstat = readl(domain_transition_base + PTSTAT);
100 mdstat = readl(control_base + MDSTAT);
108 u32 mdstat = readl(data->control_base + MDSTAT);
/linux-master/drivers/mailbox/
H A Darmada-37xx-rwtm-mailbox.c49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS);
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i));
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET);
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS);
117 reg = readl(mbox->base + RWTM_HOST_INT_MASK);
130 reg = readl(mbox->base + RWTM_HOST_INT_MASK);
/linux-master/drivers/clk/socfpga/
H A Dclk-gate-s10.c30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
60 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
67 second_bypass = readl(socfpgaclk->bypass_reg -
90 parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
97 second_bypass = readl(socfpgaclk->bypass_reg -
/linux-master/drivers/clk/imx/
H A Dclk-gate-93.c52 val = readl(gate->reg + AUTHEN_OFFSET);
57 val = readl(gate->reg + DIRECT_OFFSET);
103 u32 val = readl(gate->reg + AUTHEN_OFFSET);
106 val = readl(gate->reg + LPM_CUR_OFFSET);
110 val = readl(gate->reg);
187 authen = readl(reg + AUTHEN_OFFSET);
/linux-master/drivers/clocksource/
H A Dtimer-npcm7xx.c61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
115 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
178 val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
H A Dtimer-sun4i.c50 u32 old = readl(base + TIMER_CNTVAL_REG(1));
52 while ((old - readl(base + TIMER_CNTVAL_REG(1))) < TIMER_SYNC_TICKS)
58 u32 val = readl(base + TIMER_CTL_REG(timer));
72 u32 val = readl(base + TIMER_CTL_REG(timer));
165 return ~readl(timer_of_base(&to) + TIMER_CNTVAL_REG(1));
214 val = readl(timer_of_base(&to) + TIMER_IRQ_EN_REG);

Completed in 338 milliseconds

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