/linux-master/sound/soc/fsl/ |
H A D | fsl_rpmsg.c | 44 struct clk *p = rpmsg->mclk, *pll = NULL, *npll = NULL; local 48 /* Get current pll parent */ 54 pll = pp; 60 /* Switch to another pll parent if needed. */ 61 if (pll) { 63 if (!clk_is_match(pll, npll)) {
|
/linux-master/drivers/clk/imx/ |
H A D | Makefile | 13 mxc-clk-objs += clk-frac-pll.o 24 mxc-clk-objs += clk-sscg-pll.o
|
/linux-master/drivers/gpu/drm/radeon/ |
H A D | atombios_crtc.c | 456 * again can cause display problems if the pll is already 469 /* one other crtc is using this pll don't turn 573 /* reset the pll flags */ 648 /* adjust pll for deep color modes */ 1063 struct radeon_pll *pll; local 1074 pll = &rdev->clock.p1pll; 1077 pll = &rdev->clock.p2pll; 1082 pll = &rdev->clock.dcpll; 1086 /* update pll params */ 1087 pll 1870 int pll; local [all...] |
H A D | radeon_legacy_crtc.c | 751 struct radeon_pll *pll; local 774 pll = &rdev->clock.p2pll; 776 pll = &rdev->clock.p1pll; 778 pll->flags = RADEON_PLL_LEGACY; 781 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 783 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 795 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; 810 pll->flags |= RADEON_PLL_USE_REF_DIV; 818 radeon_compute_pll_legacy(pll, mode->clock, 849 pll_gain = radeon_compute_pll_gain(pll [all...] |
/linux-master/drivers/net/dsa/sja1105/ |
H A D | sja1105_clocking.c | 691 struct sja1105_cgu_pll_ctrl pll = {0}; local 705 pll.pllclksrc = 0xA; 706 pll.msel = 0x1; 707 pll.autoblock = 0x1; 708 pll.psel = 0x1; 709 pll.direct = 0x0; 710 pll.fbsel = 0x1; 711 pll.bypass = 0x0; 712 pll.pd = 0x1; 714 sja1105_cgu_pll_control_packing(packed_buf, &pll, PAC [all...] |
/linux-master/drivers/video/fbdev/core/ |
H A D | svgalib.c | 383 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node) argument 390 ar = pll->r_max; 400 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) { 406 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max)) 414 am = pll->m_min; 415 an = pll->n_min; 417 while ((am <= pll->m_max) && (an <= pll [all...] |
/linux-master/drivers/video/fbdev/aty/ |
H A D | atyfb_base.c | 328 static int pll; variable 386 int pll, mclk, xclk, ecp_max; member in struct:__anon1367 473 par->pll_limits.pll_max = aty_chips[i].pll; 601 par->pll.ct.xres = 0; 605 par->pll.ct.xres = var->xres; 1329 var->bits_per_pixel, &par->pll); 1348 par->dac_ops->set_dac(info, &par->pll, 1350 par->pll_ops->set_pll(info, &par->pll); 1354 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll); 1476 /* dump non shadow CRTC, pll, LC 1541 union aty_pll pll; local 1863 union aty_pll *pll = &par->pll; local 1888 union aty_pll *pll = &par->pll; local [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
H A D | nv04.c | 31 #include <subdev/bios/pll.h> 32 #include <subdev/clk/pll.h> 133 * stage pll 150 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; local 154 if (oldpll == pll) 178 nvkm_wr32(device, reg, pll); 189 if (ss) /* single stage pll mode */
|
/linux-master/drivers/video/fbdev/riva/ |
H A D | riva_hw.c | 618 unsigned int M, N, P, pll, MClk; local 620 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 621 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 802 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local 804 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 805 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 1 1051 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local 1097 unsigned int M, N, P, pll, MClk, NVClk; local [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | gk104.c | 26 #include "pll.h" 30 #include <subdev/bios/pll.h> 60 read_pll(struct gk104_clk *clk, u32 pll) argument 63 u32 ctrl = nvkm_rd32(device, pll + 0x00); 64 u32 coef = nvkm_rd32(device, pll + 0x04); 74 switch (pll) { 86 fN = nvkm_rd32(device, pll + 0x10) >> 16; 92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); 458 { 0x00ff, gk104_clk_prog_2 }, /* (maybe) program pll */ 460 { 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mod [all...] |
H A D | nv50.c | 25 #include "pll.h" 29 #include <subdev/bios/pll.h> 69 nvkm_error(subdev, "ref: bad pll %06x\n", base); 97 nvkm_error(subdev, "ref: bad pll %06x\n", base); 147 nvkm_error(subdev, "bad pll %06x\n", base); 329 struct nvbios_pll pll; local 332 ret = nvbios_pll_parse(subdev->device->bios, reg, &pll); 336 pll.vco2.max_freq = 0; 337 pll.refclk = read_pll_ref(clk, reg); 338 if (!pll [all...] |
H A D | gf100.c | 26 #include "pll.h" 29 #include <subdev/bios/pll.h> 59 read_pll(struct gf100_clk *clk, u32 pll) argument 62 u32 ctrl = nvkm_rd32(device, pll + 0x00); 63 u32 coef = nvkm_rd32(device, pll + 0x04); 72 switch (pll) { 88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); 424 { gf100_clk_prog_2 }, /* (maybe) program pll */ 425 { gf100_clk_prog_3 }, /* (maybe) select pll mode */
|
/linux-master/drivers/mfd/ |
H A D | twl6040.c | 323 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; 354 if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) { 380 if (pll_id != twl6040->pll) { 409 if (twl6040->pll == pll_id) 475 if (pll_id != twl6040->pll) 497 dev_err(twl6040->dev, "unknown pll id %d\n", pll_id); 503 twl6040->pll = pll_id; 514 return twl6040->pll;
|
/linux-master/drivers/net/wireless/ath/ath9k/ |
H A D | ar5008_phy.c | 916 u32 pll; local 918 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 921 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 923 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 926 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); 928 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); 930 return pll; 936 u32 pll; local 938 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 941 pll | [all...] |
/linux-master/drivers/accel/ivpu/ |
H A D | ivpu_hw_40xx.c | 230 hw->pll.min_ratio = clamp_t(u8, ivpu_pll_min_ratio, fuse_min_ratio, fuse_max_ratio); 231 hw->pll.max_ratio = clamp_t(u8, ivpu_pll_max_ratio, hw->pll.min_ratio, fuse_max_ratio); 232 hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); 241 u16 target_ratio = hw->pll.pn_ratio; 247 ret = ivpu_pll_cmd_send(vdev, hw->pll.min_ratio, hw->pll.max_ratio, 728 hw->pll [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | atombios_crtc.c | 253 * again can cause display problems if the pll is already 266 /* one other crtc is using this pll don't turn 356 /* adjust pll for deep color modes */ 826 struct amdgpu_pll *pll; local 836 pll = &adev->clock.ppll[0]; 839 pll = &adev->clock.ppll[1]; 844 pll = &adev->clock.ppll[2]; 848 /* update pll params */ 849 pll->flags = amdgpu_crtc->pll_flags; 850 pll [all...] |
/linux-master/drivers/clk/qcom/ |
H A D | Makefile | 6 clk-qcom-y += clk-alpha-pll.o 7 clk-qcom-y += clk-pll.o 29 obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o 60 obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o 61 obj-$(CONFIG_QCOM_A7PLL) += a7-pll.o
|
/linux-master/drivers/ptp/ |
H A D | ptp_clockmatrix.c | 502 u8 pll, 516 switch (pll) { 578 if (pll == 5 && qn_plus_1 != 0) { 600 if (pll == 6 && qn_plus_1 != 0) { 631 u8 pll; local 658 for (pll = 0; pll < 8; pll++) { 662 if (pll < 4) { 663 /* First 4 pll ha 501 _sync_pll_output(struct idtcm *idtcm, u8 pll, u8 sync_src, u8 qn, u8 qn_plus_1) argument 1183 set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll) argument [all...] |
H A D | ptp_clockmatrix.h | 108 u8 pll; member in struct:idtcm_channel
|
/linux-master/arch/m68k/coldfire/ |
H A D | m528x.c | 30 DEFINE_CLK(pll, "pll.0", MCF_CLK); 34 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
|
H A D | m527x.c | 29 DEFINE_CLK(pll, "pll.0", MCF_CLK); 33 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
|
H A D | m5249.c | 25 DEFINE_CLK(pll, "pll.0", MCF_CLK); 29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
|
/linux-master/drivers/clk/starfive/ |
H A D | clk-starfive-jh71x0.h | 117 struct clk_hw *pll[3]; member in struct:jh71x0_clk_priv
|
/linux-master/drivers/phy/rockchip/ |
H A D | phy-rockchip-inno-dsidphy.c | 223 } pll; member in struct:inno_dsidphy 358 inno->pll.prediv = best_prediv; 359 inno->pll.fbdiv = best_fbdiv; 360 inno->pll.rate = best_freq; 385 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 387 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); 389 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 414 txbyteclkhs = inno->pll.rate / 8; 457 if (inno->pll.rate <= timings[i].rate)
|
/linux-master/sound/soc/ti/ |
H A D | j721e-evm.c | 561 struct clk *pll; local 565 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_44100]); 566 if (IS_ERR_OR_NULL(pll)) { 570 priv->pll_rates[J721E_CLK_PARENT_44100] = clk_get_rate(pll); 571 clk_put(pll); 574 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_48000]); 575 if (IS_ERR_OR_NULL(pll)) { 579 priv->pll_rates[J721E_CLK_PARENT_48000] = clk_get_rate(pll); 580 clk_put(pll);
|