Searched refs:mux (Results 176 - 200 of 399) sorted by relevance

1234567891011>>

/linux-master/sound/soc/codecs/
H A Dmt6358.c1075 /* HPR/HPL mux to open */
1276 /* HPR/HPL mux to open */
1279 /* LOL mux to open */
1359 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); local
1362 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1366 mux);
1378 priv->mux_select[MUX_HP_L] = mux;
1380 if (mux == HP_MUX_HP)
1382 else if (mux == HP_MUX_HPSPK)
1402 priv->mux_select[MUX_HP_L] = mux;
1900 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); local
1946 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); local
1962 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); local
1978 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); local
1994 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); local
[all...]
/linux-master/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier.h159 #define __UNIPHIER_PINCTRL_GROUP(grp, mux) \
164 .muxvals = mux, \
/linux-master/drivers/clk/at91/
H A DMakefile16 obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
/linux-master/drivers/gpu/drm/meson/
H A Dmeson_vpp.c36 void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux) argument
38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
/linux-master/drivers/clk/st/
H A Dclk-flexgen.c35 struct clk_mux mux; member in struct:flexgen
99 struct clk_hw *mux_hw = &flexgen->mux.hw;
109 struct clk_hw *mux_hw = &flexgen->mux.hw;
231 fgxbar->mux.lock = lock;
232 fgxbar->mux.mask = BIT(6) - 1;
233 fgxbar->mux.reg = xbar_reg;
234 fgxbar->mux.shift = xbar_shift;
235 fgxbar->mux.table = NULL;
/linux-master/drivers/clk/
H A Dclk-cdce706.c74 unsigned mux; member in struct:cdce706_hw_data
169 "%s, pll: %d, mux: %d, mul: %u, div: %u\n",
170 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div);
172 if (!hwd->mux) {
523 unsigned mux; local
525 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux);
544 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);
546 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i,
547 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);
[all...]
/linux-master/include/net/
H A Dkcm.h60 struct kcm_mux *mux; member in struct:kcm_sock
92 struct kcm_mux *mux; member in struct:kcm_psock
154 spinlock_t lock ____cacheline_aligned_in_smp; /* TX and mux locking */
170 /* Save psock statistics in the mux when psock is being unattached. */
184 /* Save psock statistics in the mux when psock is being unattached. */
/linux-master/drivers/pinctrl/freescale/
H A Dpinctrl-scu.c92 unsigned int mux = configs[0]; local
115 * Set mux and conf together in one IPC call
121 val |= mux << BP_PAD_CTL_IFMUX;
/linux-master/drivers/clk/sunxi-ng/
H A Dccu-sun50i-a100-r.c29 .mux = {
64 .mux = {
121 24, 1, /* mux */
H A Dccu_nkm.c165 static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux, argument
201 return ccu_mux_helper_determine_rate(&nkm->common, &nkm->mux,
248 return ccu_mux_helper_get_parent(&nkm->common, &nkm->mux);
255 return ccu_mux_helper_set_parent(&nkm->common, &nkm->mux, index);
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_gpio.h78 * Some GPIOs have HW mux which allows to choose
101 uint32_t mux; member in struct:hw_gpio::__anon2485
H A Dhw_generic.c76 REG_UPDATE_2(mux,
/linux-master/drivers/pinctrl/bcm/
H A Dpinctrl-bcm6318.c305 #define BCM6318_MUX_FUN(n, mux) \
310 .mux_val = mux, \
389 unsigned int mode, unsigned int mux)
399 mux << ((pin % 16) * 2));
430 /* GPIOs 0-12 use mux 0 as GPIO function */
433 /* GPIOs 13-41 use mux 3 as GPIO function */
388 bcm6318_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin, unsigned int mode, unsigned int mux) argument
/linux-master/drivers/clk/ingenic/
H A Dcgu.h71 * struct ingenic_cgu_mux_info - information about a clock mux
72 * @reg: offset of the mux control register within the CGU
73 * @shift: number of bits to shift the mux value by (ie. the index of
74 * the lowest bit of the mux value within its control register)
75 * @bits: the size of the mux value in bits
152 * @mux: information valid if type includes CGU_CLK_MUX
181 struct ingenic_cgu_mux_info mux; member in struct:ingenic_cgu_clk_info::__anon243::__anon244
/linux-master/arch/arm/mach-omap1/
H A DMakefile7 obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
/linux-master/drivers/net/mdio/
H A Dmdio-mux-gpio.c8 #include <linux/mdio-mux.h>
73 .compatible = "mdio-mux-gpio",
77 .compatible = "cavium,mdio-mux-sn74cbtlv3253",
85 .name = "mdio-mux-gpio",
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dpriv.h33 const struct nvkm_specmux *mux; member in struct:nvkm_specsrc
/linux-master/drivers/clk/imx/
H A DMakefile12 mxc-clk-objs += clk-fixup-mux.o
25 mxc-clk-objs += clk-gpr-mux.o
/linux-master/drivers/clk/qcom/
H A Dclk-cbf-8996.c109 struct clk_cbf_8996_mux *mux = to_clk_cbf_8996_mux(clkr); local
112 regmap_read(clkr->regmap, mux->reg, &val);
120 struct clk_cbf_8996_mux *mux = to_clk_cbf_8996_mux(clkr); local
125 return regmap_update_bits(clkr->regmap, mux->reg, CBF_MUX_PARENT_MASK, val);
/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_kms.c255 unsigned char mux; local
273 mux = (channel == 2) ? 0 : 1;
277 VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
282 mux = 3;
284 mux = channel;
289 VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
294 mux = 3;
296 mux = channel;
301 VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
307 mux
[all...]
/linux-master/drivers/net/usb/
H A Dhso.c526 /* converts mux value to a port spec value */
527 static u32 hso_mux_to_port(int mux) argument
531 switch (mux) {
553 /* converts port spec value to a mux value */
582 int mux)
586 port = hso_mux_to_port(mux);
1814 "ERROR: mux'd reads with multiple buffers "
2585 /* Frees an AT channel ( goes for both mux and non-mux ) */
2697 struct hso_shared_int *mux)
580 get_serial_by_shared_int_and_type( struct hso_shared_int *shared_int, int mux) argument
2695 hso_create_mux_serial_device(struct usb_interface *interface, int port, struct hso_shared_int *mux) argument
2747 hso_free_shared_int(struct hso_shared_int *mux) argument
2758 struct hso_shared_int *mux = kzalloc(sizeof(*mux), GFP_KERNEL); local
2868 int mux, i, if_num, port_spec; local
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atpx_handler.c74 u16 mux; member in struct:atpx_mux
211 /* if separate mux flag is set, mux controls are required */
216 /* if any outputs are muxed, mux controls are required */
332 * amdgpu_atpx_switch_disp_mux - switch display mux
335 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
338 * switch the display mux between the discrete GPU and integrated GPU
350 input.mux = mux_id;
364 * amdgpu_atpx_switch_i2c_mux - switch i2c/hpd mux
367 * @mux_id: mux stat
[all...]
/linux-master/drivers/gpu/ipu-v3/
H A Dipu-prg.c205 u32 val, mux; local
210 /* configure the PRE to PRG channel mux */
212 mux = (prg->id << 1) | (prg_chan - 1);
214 0x3 << shift, mux << shift);
216 /* check other mux, must not point to same channel */
219 if (((val >> shift) & 0x3) == mux) {
222 (mux ^ 0x1) << shift);
/linux-master/drivers/comedi/drivers/
H A Dpcl711.c214 unsigned int mux = 0; local
222 mux |= PCL711_MUX_DIFF;
225 mux |= PCL711_MUX_CS0;
227 mux |= PCL711_MUX_CS1;
230 outb(mux | PCL711_MUX_CHAN(chan), dev->iobase + PCL711_MUX_REG);
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_atpx_handler.c61 u16 mux; member in struct:atpx_mux
191 /* if separate mux flag is set, mux controls are required */
196 /* if any outputs are muxed, mux controls are required */
301 * radeon_atpx_switch_disp_mux - switch display mux
304 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
307 * switch the display mux between the discrete GPU and integrated GPU
319 input.mux = mux_id;
333 * radeon_atpx_switch_i2c_mux - switch i2c/hpd mux
336 * @mux_id: mux stat
[all...]

Completed in 366 milliseconds

1234567891011>>