Searched refs:mcr (Results 51 - 75 of 167) sorted by relevance

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/linux-master/drivers/usb/serial/
H A Dch341.c97 u8 mcr; member in struct:ch341_private
333 r = ch341_set_handshake(dev, priv->mcr);
432 priv->mcr |= CH341_BIT_RTS | CH341_BIT_DTR;
434 priv->mcr &= ~(CH341_BIT_RTS | CH341_BIT_DTR);
436 ch341_set_handshake(port->serial->dev, priv->mcr);
543 priv->mcr &= ~(CH341_BIT_DTR | CH341_BIT_RTS);
545 priv->mcr |= (CH341_BIT_DTR | CH341_BIT_RTS);
548 ch341_set_handshake(port->serial->dev, priv->mcr);
690 priv->mcr |= CH341_BIT_RTS;
692 priv->mcr |
786 u8 mcr; local
[all...]
H A Dark3116.c69 __u32 mcr; /* modem control register value */ member in struct:ark3116_private
148 priv->mcr = 0;
383 ctrl = priv->mcr;
407 * in priv->mcr is actually the one that is in the hardware
413 priv->mcr |= UART_MCR_RTS;
415 priv->mcr |= UART_MCR_DTR;
417 priv->mcr |= UART_MCR_OUT1;
419 priv->mcr |= UART_MCR_OUT2;
421 priv->mcr &= ~UART_MCR_RTS;
423 priv->mcr
[all...]
H A Dwhiteheat.c144 __u8 mcr; /* FIXME: no locking on mcr */ member in struct:whiteheat_private
409 if (info->mcr & UART_MCR_DTR)
411 if (info->mcr & UART_MCR_RTS)
424 info->mcr |= UART_MCR_RTS;
426 info->mcr |= UART_MCR_DTR;
429 info->mcr &= ~UART_MCR_RTS;
431 info->mcr &= ~UART_MCR_DTR;
433 firm_set_dtr(port, info->mcr & UART_MCR_DTR);
434 firm_set_rts(port, info->mcr
[all...]
/linux-master/arch/arm/mm/
H A Dcache-v7.S44 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
64 mcr p15, 0, ip, c7, c6, 2
86 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
87 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
144 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
166 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way
180 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
201 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
202 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
217 ALT_SMP(mcr p1
[all...]
H A Dpv-fixup-asm.S24 mcr p15, 0, ip, c1, c0, 0
75 mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
76 mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
80 mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
H A Dtlb-v4.S39 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
H A Dproc-v7-3level.S87 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
131 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
/linux-master/arch/arm/mach-omap2/
H A Dsleep24xx.S54 mov r3, #0x0 @ clear for mcr call
55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
63 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
/linux-master/drivers/soc/fsl/qbman/
H A Dqman.c943 union qm_mc_result **mcr)
948 *mcr = qm_mc_result(portal);
949 if (*mcr)
1456 union qm_mc_result *mcr; local
1465 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1472 qman_cgrs_and(&rr, (struct qman_cgrs *)&mcr->querycongestion.state,
1859 union qm_mc_result *mcr; local
1938 if (!qm_mc_result_timeout(&p->p, &mcr)) {
1944 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1945 res = mcr
942 qm_mc_result_timeout(struct qm_portal *portal, union qm_mc_result **mcr) argument
1972 union qm_mc_result *mcr; local
2013 union qm_mc_result *mcr; local
2095 union qm_mc_result *mcr; local
2133 union qm_mc_result *mcr; local
2158 union qm_mc_result *mcr; local
2187 union qm_mc_result *mcr; local
2361 union qm_mc_result *mcr; local
2683 union qm_mc_result *mcr; local
[all...]
/linux-master/arch/arm/mach-spear/
H A Dheadsmp.S34 mcr p15, 0, r0, c1, c0, 1
/linux-master/arch/arm/mach-imx/
H A Dheadsmp.S21 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
/linux-master/arch/arm/mach-rockchip/
H A Dsleep.S34 mcr p15, 1, r3, c9, c0, 2
/linux-master/arch/arm/mach-socfpga/
H A Dself-refresh.S51 mcr p15, 0, r2, c15, c0, 0
118 mcr p15, 0, r2, c15, c0, 0
/linux-master/arch/arm/include/debug/
H A Dicedcc.S16 mcr p14, 0, \rd, c0, c5, 0
43 mcr p14, 0, \rd, c8, c0, 0
70 mcr p14, 0, \rd, c1, c0, 0
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_gt_mcr.c186 static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr) argument
188 i915_reg_t r = { .reg = mcr.reg };
212 u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0; local
247 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
248 old_mcr = mcr;
250 mcr &= ~mcr_mask;
251 mcr |= mcr_ss;
252 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
257 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
258 old_mcr = mcr;
[all...]
H A Dintel_tlb.c32 if (engine->tlb_inv.mcr)
71 if (engine->tlb_inv.mcr)
/linux-master/arch/arm/kernel/
H A Dhead-nommu.S184 mcr p15, 0, r0, c1, c0, 0 @ write control reg
219 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
224 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
225 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
226 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
337 AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
350 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
351 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
364 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
365 AR_CLASS(mcr p1
[all...]
H A Diwmmxt.h43 mcr p1, 0, \src, \control, c0, 0
/linux-master/drivers/net/wan/
H A Dn2.c156 u8 mcr = inb(io + N2_MCR); local
163 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
169 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
175 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
181 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
186 outb(mcr, io + N2_MCR);
198 u8 mcr = inb(io + N2_MCR) | local
206 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
207 outb(mcr, io + N2_MCR);
220 u8 mcr local
[all...]
/linux-master/arch/arm/include/asm/
H A Dtls.h16 mcr p15, 0, \tpuser, c13, c0, 2 @ set the user r/w register
32 mcr p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
90 * thread_info upon resuming execution and the following mcr
97 asm("mcr p15, 0, %0, c13, c0, 3"
131 asm("mcr p15, 0, %0, c13, c0, 2"
/linux-master/arch/arm/lib/
H A Dcsumpartialcopyuser.S26 mcr p15, 0, ip, c3, c0, 0
40 mcr p15, 0, ip, c2, c0, 2 @ restore TTBCR
/linux-master/drivers/i2c/busses/
H A Di2c-nomadik.c350 u32 mcr = 0; local
353 mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr);
357 mcr |= FIELD_PREP(I2C_MCR_AM, 2);
367 mcr |= FIELD_PREP(I2C_MCR_EA10, slave_adr_3msb_bits);
370 mcr |= FIELD_PREP(I2C_MCR_AM, 1);
374 mcr |= FIELD_PREP(I2C_MCR_SB, 0);
378 mcr |= FIELD_PREP(I2C_MCR_OP, I2C_WRITE);
380 mcr |= FIELD_PREP(I2C_MCR_OP, I2C_READ);
384 mcr |= FIELD_PREP(I2C_MCR_STOP, 1);
386 mcr
512 u32 mcr, irq_mask; local
577 u32 mcr, irq_mask; local
[all...]
/linux-master/arch/arm/mach-pxa/
H A Dsleep.S32 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
132 mcr p14, 0, r0, c6, c0, 0
146 mcr p14, 0, r0, c6, c0, 0
170 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
/linux-master/drivers/tty/serial/8250/
H A D8250_em.c87 unsigned int ier, fcr, lcr, mcr, hcr0; local
92 mcr = serial8250_em_serial_in(p, UART_MCR);
111 mcr = value;
117 serial8250_em_serial_out_helper(p, UART_MCR, mcr);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_reg_sr.c129 "discarding save-restore reg %04lx (clear: %08x, set: %08x, masked: %s, mcr: %s): ret=%d\n",
132 str_yes_no(e->reg.mcr),
140 * Convert back from encoded value to type-safe, only to be used when reg.mcr
165 val = (reg.mcr ?
180 if (entry->reg.mcr)
280 drm_printf(p, "\tREG[0x%lx] clr=0x%08x set=0x%08x masked=%s mcr=%s\n",
283 str_yes_no(entry->reg.mcr));

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