/linux-master/arch/arm/mm/ |
H A D | tlb-v4wb.S | 37 mcr p15, 0, r3, c7, c10, 4 @ drain WB 42 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 60 mcr p15, 0, r3, c7, c10, 4 @ drain WB 63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | tlb-v4wbi.S | 36 mcr p15, 0, r3, c7, c10, 4 @ drain WB 42 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 51 mcr p15, 0, r3, c7, c10, 4 @ drain WB 54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | proc-arm740.S | 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 66 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 74 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 76 mcr p15, 0, r0, c6, c3 @ disable area 3~7 77 mcr p15, 0, r0, c6, c4 78 mcr p15, 0, r0, c6, c5 79 mcr p15, 0, r0, c6, c6 80 mcr p15, 0, r0, c6, c7 83 mcr p1 [all...] |
H A D | cache-v4wt.S | 49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 72 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 91 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 128 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 147 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 165 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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H A D | proc-feroceon.S | 74 mcr p15, 1, r0, c15, c9, 0 @ clean L2 75 mcr p15, 0, r0, c7, c10, 4 @ drain WB 81 mcr p15, 0, r0, c1, c0, 0 @ disable caches 98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 99 mcr p15, 0, ip, c7, c10, 4 @ drain WB 101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 106 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 119 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 131 mcr p1 [all...] |
H A D | cache-v4wb.S | 59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 118 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 119 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 172 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 178 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 179 mcr p15, 0, r0, c7, c10, 4 @ drain WB 200 1: mcr p1 [all...] |
H A D | proc-xscale.S | 92 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 94 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 119 mcr p15, 0, r1, c1, c0, 1 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 150 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 151 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 159 mcr p1 [all...] |
H A D | tlb-v7.S | 50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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H A D | proc-arm720.S | 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 73 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 74 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 75 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 102 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 104 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 109 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 119 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 145 mcr p1 [all...] |
H A D | cache-v4.S | 41 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 61 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache 123 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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H A D | proc-v7-2level.S | 56 mcr p15, 0, r1, c13, c0, 1 @ set context ID 58 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 106 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 147 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register 152 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
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H A D | proc-v7.S | 38 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 89 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 120 mcr p15, 0, r3, c7, c5, 0 @ ICIALLU 125 mcr p15, 0, r3, c7, c5, 6 @ flush BTAC/BTB 159 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 163 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 166 mcr p1 [all...] |
/linux-master/arch/sh/drivers/pci/ |
H A D | fixups-se7751.c | 41 unsigned long bcr1, wcr1, wcr2, wcr3, mcr; local 56 mcr = (*(volatile unsigned long*)(SH7751_MCR)); 67 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 68 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
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/linux-master/drivers/iio/adc/ |
H A D | imx93_adc.c | 104 u32 mcr, msr; local 107 mcr = readl(adc->regs + IMX93_ADC_MCR); 108 mcr |= FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); 109 writel(mcr, adc->regs + IMX93_ADC_MCR); 123 u32 mcr; local 126 mcr = readl(adc->regs + IMX93_ADC_MCR); 127 mcr &= ~FIELD_PREP(IMX93_ADC_MCR_PWDN_MASK, 1); 128 writel(mcr, adc->regs + IMX93_ADC_MCR); 133 u32 mcr; local 139 mcr 148 u32 mcr, msr; local 196 u32 imr, mcr, pcda; local [all...] |
/linux-master/drivers/gpu/drm/xe/regs/ |
H A D | xe_reg_defs.h | 32 * @mcr: register is multicast/replicated in the 39 u32 mcr:1; member in struct:xe_reg::__anon817::__anon818 131 .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \
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/linux-master/arch/arm/include/asm/ |
H A D | uaccess-asm.h | 50 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register 62 mcr p15, 0, \tmp, c3, c0, 0 79 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR 93 mcr p15, 0, \tmp, c2, c0, 2 @ write TTBCR 139 mcr p15, 0, \tmp2, c3, c0, 0 145 mcr p15, 0, \tmp2, c3, c0, 0 153 DACR( mcr p15, 0, \tmp0, c3, c0, 0) 155 PAN( mcr p15, 0, \tmp0, c2, c0, 2)
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/linux-master/arch/arm/boot/compressed/ |
H A D | head-xscale.S | 27 mcr p15, 0, r0, c7, c10, 4 @ drain WB 28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 34 mcr p15, 0, r0, c1, c0, 0
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H A D | head.S | 38 mcr p14, 0, \ch, c0, c5, 0 44 mcr p14, 0, \ch, c8, c0, 0 50 mcr p14, 0, \ch, c1, c0, 0 145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR 731 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 732 mcr p15, 0, r0, c6, c7, 1 735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 740 mcr p1 [all...] |
H A D | head-sa1100.S | 37 mcr p15, 0, r0, c7, c10, 4 @ drain WB 38 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 44 mcr p15, 0, r0, c1, c0, 0
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/linux-master/drivers/mtd/nand/raw/ |
H A D | txx9ndfmc.c | 113 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local 115 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); 118 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); 138 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local 140 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); 141 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; 142 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; 144 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; 146 mcr &= ~TXX9_NDFMCR_CS_MASK; 147 mcr | 172 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local 211 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); local [all...] |
/linux-master/arch/x86/platform/intel/ |
H A D | iosf_mbi.c | 39 static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr) argument 53 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); 68 static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr) argument 86 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); 99 u32 mcr, mcrx; local 109 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); 113 ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr); 122 u32 mcr, mcrx; local 132 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); 136 ret = iosf_mbi_pci_write_mdr(mcrx, mcr, md 145 u32 mcr, mcrx; local [all...] |
/linux-master/drivers/tty/serial/8250/ |
H A D | 8250.h | 221 int mcr = 0; local 224 mcr |= UART_MCR_RTS; 226 mcr |= UART_MCR_DTR; 228 mcr |= UART_MCR_OUT1; 230 mcr |= UART_MCR_OUT2; 232 mcr |= UART_MCR_LOOP; 234 return mcr; 237 static inline int serial8250_MCR_to_TIOCM(int mcr) argument 241 if (mcr & UART_MCR_RTS) 243 if (mcr [all...] |
/linux-master/arch/arm/mach-sunxi/ |
H A D | headsmp.S | 39 mcr p15, 1, r1, c15, c0, 4 47 mcr p15, 1, r1, c15, c0, 0 53 mcr p15, 1, r1, c9, c0, 2
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/linux-master/arch/sh/boards/mach-hp6xx/ |
H A D | pm.c | 41 u16 frqcr, mcr; local 64 mcr = __raw_readw(MCR); 65 __raw_writew(mcr & ~MCR_RFSH, MCR); 76 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
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/linux-master/drivers/tty/serial/ |
H A D | sunplus-uart.c | 101 unsigned int mcr = readl(port->membase + SUP_UART_MCR); local 104 mcr |= UART_MCR_DTR; 106 mcr &= ~UART_MCR_DTR; 109 mcr |= UART_MCR_RTS; 111 mcr &= ~UART_MCR_RTS; 114 mcr |= SUP_UART_MCR_DCD; 116 mcr &= ~SUP_UART_MCR_DCD; 119 mcr |= SUP_UART_MCR_RI; 121 mcr &= ~SUP_UART_MCR_RI; 124 mcr | 133 unsigned int mcr, ret = 0; local [all...] |