/linux-master/drivers/gpu/drm/bridge/ |
H A D | ti-sn65dsi86.c | 255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 716 /* TODO: setting to 4 MIPI lanes always for now */ 717 dsi->lanes = 4; 833 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 1098 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1186 /* Num lanes to 0 as per power sequencing in data sheet */ 1248 * data-lanes but not lane-polarities but not vice versa. 1257 of_property_read_u32_array(endpoint, "data-lanes", 1267 * Convert into register format. Loop over all lanes even if 1268 * data-lanes ha [all...] |
H A D | tc358764.c | 225 /* enable four data lanes and clock lane */ 357 dsi->lanes = 4;
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/linux-master/drivers/media/i2c/ccs/ |
H A D | ccs-core.c | 402 sensor->pll.csi2.lanes : 1) << 1642 rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg.lanes - 1); 3113 hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; 3117 hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes; 3124 hwcfg->lanes = 1; 3440 sensor->pll.csi2.lanes = sensor->hwcfg.lanes; 3452 sensor->pll.vt_lanes = sensor->pll.csi2.lanes; 3453 sensor->pll.op_lanes = sensor->pll.csi2.lanes;
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/linux-master/drivers/media/pci/intel/ipu3/ |
H A D | ipu3-cio2.h | 168 #define CIO2_PBM_ARB_CTRL_LANES_DIV 0U /* 4-4-2-2 lanes */ 341 u32 lanes; member in struct:csi2_bus_info
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/linux-master/drivers/gpu/drm/rockchip/ |
H A D | cdn-dp-reg.c | 357 int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip) argument 363 msg[1] = lanes | SCRAMBLER_EN; 563 DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->max_rate, 667 "tu error, clk:%d, lanes:%d, rate:%d\n",
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/linux-master/drivers/gpu/drm/sprd/ |
H A D | sprd_dsi.c | 444 * Configure timers for data lanes and/or clock lane to return to LP when 520 ratio_x1000 / dsi->slave->lanes / 1000; 763 writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
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/linux-master/drivers/phy/freescale/ |
H A D | phy-fsl-imx8-mipi-dphy.c | 470 if (lvds_cfg->lanes != 4) { 471 dev_err(&phy->dev, "Invalid LVDS data lanes: %u\n", lvds_cfg->lanes);
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/linux-master/drivers/infiniband/core/ |
H A D | verbs.c | 1886 static void ib_get_width_and_speed(u32 netdev_speed, u32 lanes, argument 1889 if (!lanes) { 1922 switch (lanes) { 1942 switch (netdev_speed / lanes) { 1998 ib_get_width_and_speed(netdev_speed, lksettings.lanes,
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/linux-master/drivers/net/ethernet/hisilicon/hns3/ |
H A D | hns3_ethtool.c | 755 &cmd->lanes); 854 cmd->base.duplex == duplex && cmd->lanes == lane_num) 891 if (cmd->lanes && !hnae3_ae_dev_lane_num_supported(ae_dev)) 895 "set link(%s): autoneg=%u, speed=%u, duplex=%u, lanes=%u\n", 898 cmd->lanes); 936 cmd->base.duplex, (u8)(cmd->lanes));
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/linux-master/drivers/gpu/drm/bridge/cadence/ |
H A D | cdns-mhdp8546-core.c | 504 dev_err(mhdp->dev, "invalid number of lanes: %u\n", nlanes); 900 phy_cfg.dp.lanes = mhdp->link.num_lanes; 1037 dev_dbg(mhdp->dev, "%s, %u lanes, %u Mbps, vs %s, pe %s\n", 1072 phy_cfg.dp.lanes = mhdp->link.num_lanes; 1193 phy_cfg.dp.lanes = mhdp->link.num_lanes; 1282 "Reducing lanes number during CR phase\n"); 1300 "Reducing lanes number during EQ phase\n"); 1595 unsigned int lanes, unsigned int rate) 1608 max_bw = lanes * rate; 2203 dev_err(mhdp->dev, "%s: Not enough BW for %s (%u lanes a 1593 cdns_mhdp_bandwidth_ok(struct cdns_mhdp_device *mhdp, const struct drm_display_mode *mode, unsigned int lanes, unsigned int rate) argument [all...] |
/linux-master/drivers/gpu/drm/radeon/ |
H A D | r600_dpm.c | 1360 u8 r600_encode_pci_lane_width(u32 lanes) argument 1366 if (lanes > 16) 1369 return encoded_lanes[lanes];
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | r535.c | 936 r535_dp_drive(struct nvkm_outp *outp, u8 lanes, u8 pe[4], u8 vs[4]) argument 947 ctrl->numLanes = lanes; 948 for (int i = 0; i < lanes; i++)
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/linux-master/drivers/media/pci/intel/ipu6/ |
H A D | ipu6-isys-video.c | 754 unsigned int bpp, lanes; local 778 lanes = csi2->nlanes; 783 pixel_rate = mul_u64_u32_div(link_freq, lanes * 2, bpp);
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/linux-master/drivers/gpu/drm/panel/ |
H A D | panel-raydium-rm67191.c | 578 ret = of_property_read_u32(np, "dsi-lanes", &dsi->lanes); 580 dev_err(dev, "Failed to get dsi-lanes property (%d)\n", ret);
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H A D | panel-samsung-s6e63j0x03.c | 447 dsi->lanes = 1;
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H A D | panel-magnachip-d53e6ea8966.c | 423 db->dsi_dev->lanes = 2;
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H A D | panel-dsi-cm.c | 557 dsi->lanes = 2;
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H A D | panel-feixin-k101-im2ba02.c | 50 /* Lane number, 0x02 - 3 lanes, 0x03 - 4 lanes */ 477 dsi->lanes = 4;
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H A D | panel-raydium-rm68200.c | 160 dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */ 353 dsi->lanes = 2;
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H A D | panel-orisetech-otm8009a.c | 448 dsi->lanes = 2;
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H A D | panel-newvision-nv3051d.c | 389 dsi->lanes = 4;
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/linux-master/drivers/gpu/drm/bridge/imx/ |
H A D | imx8qxp-ldb.c | 70 phy_cfg->lanes = 4;
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H A D | imx8qm-ldb.c | 73 phy_cfg->lanes = 4;
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/linux-master/drivers/thunderbolt/ |
H A D | dma_test.c | 405 DMA_TEST_DEBUGFS_ATTR(lanes, lanes_get, lanes_validate, lanes_set); 543 dev_err(&svc->dev, "failed to set lanes\n"); 626 debugfs_create_file("lanes", 0600, dt->debugfs_dir, svc, &lanes_fops);
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/linux-master/drivers/net/ethernet/mellanox/mlxsw/ |
H A D | core.h | 262 bool splittable, u32 lanes,
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