Searched refs:hwirq (Results 26 - 50 of 384) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-xilinx-intc.c67 unsigned long mask = BIT(d->hwirq);
69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
86 xintc_write(irqc, CIE, BIT(d->hwirq));
93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
94 xintc_write(irqc, IAR, BIT(d->hwirq));
100 unsigned long mask = BIT(d->hwirq);
102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
145 u32 hwirq = xintc_read(irqc, IVR); local
147 if (hwirq
157 u32 hwirq; local
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H A Dirq-pruss-intc.c173 * @hwirq: the system event number
178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq) argument
186 intc->event_channel[hwirq].ref_count++;
188 ch = intc->event_channel[hwirq].value;
191 pruss_intc_update_cmr(intc, hwirq, ch);
193 reg_idx = hwirq / 32;
194 val = BIT(hwirq % 32);
208 hwirq, ch, host);
216 * @hwirq: the system event number
222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq) argument
293 unsigned int hwirq = data->hwirq; local
301 unsigned int hwirq = data->hwirq; local
309 unsigned int hwirq = data->hwirq; local
466 unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq)); local
491 int hwirq, err; local
606 unsigned int hwirq; local
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H A Dirq-sni-exiu.c44 writel(BIT(d->hwirq), data->base + EIREQCLR);
58 writel(BIT(d->hwirq), data->base + EIREQCLR);
68 val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
78 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
89 writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
91 val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
103 val |= BIT(d->hwirq);
105 val &= ~BIT(d->hwirq);
110 val &= ~BIT(d->hwirq);
113 val |= BIT(d->hwirq);
138 exiu_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
169 irq_hw_number_t hwirq; local
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H A Dirq-sifive-plic.c93 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) argument
95 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
96 u32 hwirq_mask = 1 << (hwirq % 32);
104 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) argument
109 __plic_toggle(handler->enable_base, hwirq, enable);
121 plic_toggle(handler, d->hwirq, enable);
139 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
146 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
154 plic_toggle(handler, d->hwirq, 1);
155 writel(d->hwirq, handle
308 plic_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
320 plic_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
337 irq_hw_number_t hwirq; local
371 irq_hw_number_t hwirq; local
492 irq_hw_number_t hwirq; local
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H A Dirq-mvebu-odmi.c56 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME))
59 odmi = &odmis[d->hwirq >> NODMIS_SHIFT];
60 odmin = d->hwirq & NODMIS_MASK;
84 unsigned int hwirq, odmin; local
88 hwirq = find_first_zero_bit(odmis_bm, NODMIS_PER_FRAME * odmis_count);
89 if (hwirq >= NODMIS_PER_FRAME * odmis_count) {
94 __set_bit(hwirq, odmis_bm);
97 odmi = &odmis[hwirq >> NODMIS_SHIFT];
98 odmin = hwirq & NODMIS_MASK;
119 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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H A Dirq-loongson-pch-msi.c69 int hwirq, int num_req)
71 int first = hwirq - priv->irq_first;
85 msg->data = data->hwirq;
104 unsigned int virq, int hwirq)
110 fwspec.param[0] = hwirq;
120 int hwirq, err, i; local
122 hwirq = pch_msi_allocate_hwirq(priv, nr_irqs);
123 if (hwirq < 0)
124 return hwirq;
127 err = pch_msi_parent_domain_alloc(domain, virq + i, hwirq
68 pch_msi_free_hwirq(struct pch_msi_data *priv, int hwirq, int num_req) argument
103 pch_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq) argument
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H A Dirq-xtensa-pic.c25 * two cell bindings. First cell value maps directly to the hwirq number.
26 * Second cell if present specifies whether hwirq number is external (1) or
49 irq_mask &= ~BIT(d->hwirq);
58 irq_mask |= BIT(d->hwirq);
64 xtensa_set_sr(BIT(d->hwirq), intclear);
69 unsigned int mask = BIT(d->hwirq);
H A Dirq-crossbar.c75 irq_hw_number_t hwirq)
87 cb->irq_map[i] = hwirq;
106 cb->write(i, hwirq);
115 irq_hw_number_t hwirq; local
123 hwirq = fwspec->param[1];
124 if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
128 int err = allocate_gic_irq(d, virq + i, hwirq + i);
133 irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
162 cb->irq_map[d->hwirq] = IRQ_FREE;
163 cb->write(d->hwirq, c
74 allocate_gic_irq(struct irq_domain *domain, unsigned virq, irq_hw_number_t hwirq) argument
168 crossbar_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-vf610-mscm-ir.c88 irq_hw_number_t hwirq = data->hwirq; local
92 irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
98 chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
105 irq_hw_number_t hwirq = data->hwirq; local
108 writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
128 irq_hw_number_t hwirq; local
138 hwirq = fwspec->param[0];
140 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq
160 vf610_mscm_ir_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-mst-intc.c41 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
46 mask = 1 << (hwirq % 16);
47 offset += (hwirq / 16) * 4;
57 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
62 mask = 1 << (hwirq % 16);
63 offset += (hwirq / 16) * 4;
178 unsigned long *hwirq,
194 *hwirq = fwspec->param[1];
206 irq_hw_number_t hwirq; local
218 hwirq
176 mst_intc_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-mips-cpu.c42 set_c0_status(IE_SW0 << d->hwirq);
48 clear_c0_status(IE_SW0 << d->hwirq);
71 clear_c0_cause(C_SW0 << d->hwirq);
84 clear_c0_cause(C_SW0 << d->hwirq);
93 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
104 write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
187 unsigned int i, hwirq; local
191 hwirq = find_first_zero_bit(state->allocated, 2);
192 if (hwirq == 2)
194 bitmap_set(state->allocated, hwirq,
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H A Dirq-csky-mpintc.c85 setup_trigger(d->hwirq, __trigger[d->hwirq]);
87 writel_relaxed(d->hwirq, reg_base + INTCL_SENR);
94 writel_relaxed(d->hwirq, reg_base + INTCL_CENR);
101 writel_relaxed(d->hwirq, reg_base + INTCL_CACR);
108 __trigger[d->hwirq] = 0;
111 __trigger[d->hwirq] = 1;
114 __trigger[d->hwirq] = 2;
117 __trigger[d->hwirq] = 3;
132 unsigned int offset = 4 * (d->hwirq
175 csky_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
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H A Dirq-lpc32xx.c49 u32 val, mask = BIT(d->hwirq);
58 u32 val, mask = BIT(d->hwirq);
67 u32 mask = BIT(d->hwirq);
75 u32 val, mask = BIT(d->hwirq);
143 u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq; local
145 while (hwirq) {
146 irq = __ffs(hwirq);
147 hwirq &= ~BIT(irq);
156 u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq; local
160 while (hwirq) {
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/linux-master/drivers/gpio/
H A Dgpio-hlwd.c66 int hwirq; local
101 for_each_set_bit(hwirq, &pending, 32)
102 generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq);
112 iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
124 mask &= ~BIT(data->hwirq);
140 mask |= BIT(data->hwirq);
151 static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq, argument
158 state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
159 level &= ~BIT(hwirq);
160 level |= state ^ BIT(hwirq);
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/linux-master/arch/powerpc/platforms/4xx/
H A Dhsta_msi.c42 int irq, hwirq; local
59 hwirq = ppc4xx_hsta_msi.irq_map[irq];
60 if (!hwirq) {
76 pr_debug("%s: Setup irq %d (0x%0llx)\n", __func__, hwirq,
79 if (irq_set_msi_desc(hwirq, entry)) {
81 "%s: Invalid hwirq %d specified in device tree\n",
82 __func__, hwirq);
86 pci_write_msi_msg(hwirq, &msg);
92 static int hsta_find_hwirq_offset(int hwirq) argument
96 /* Find the offset given the hwirq */
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/linux-master/drivers/mailbox/
H A Dqcom-ipcc.c75 u32 hwirq; local
79 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
80 if (hwirq == IPCC_NO_PENDING_IRQ)
83 virq = irq_find_mapping(ipcc->irq_domain, hwirq);
84 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
94 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); local
96 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
102 irq_hw_number_t hwirq = irqd_to_hwirq(irqd); local
104 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
150 u32 hwirq; local
259 u32 hwirq; local
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/linux-master/kernel/irq/
H A Dirqdomain.c390 * @first_hwirq: first hwirq number to use for the translation. Should normally
510 irq_hw_number_t hwirq)
517 if (hwirq < domain->revmap_size)
518 rcu_assign_pointer(domain->revmap[hwirq], NULL);
520 radix_tree_delete(&domain->revmap_tree, hwirq);
524 irq_hw_number_t hwirq,
536 if (hwirq < domain->revmap_size)
537 rcu_assign_pointer(domain->revmap[hwirq], irq_data);
539 radix_tree_insert(&domain->revmap_tree, hwirq, irq_data);
545 irq_hw_number_t hwirq; local
509 irq_domain_clear_mapping(struct irq_domain *domain, irq_hw_number_t hwirq) argument
523 irq_domain_set_mapping(struct irq_domain *domain, irq_hw_number_t hwirq, struct irq_data *irq_data) argument
578 irq_domain_associate_locked(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq) argument
620 irq_domain_associate(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq) argument
691 irq_create_mapping_affinity_locked(struct irq_domain *domain, irq_hw_number_t hwirq, const struct irq_affinity_desc *affinity) argument
730 irq_create_mapping_affinity(struct irq_domain *domain, irq_hw_number_t hwirq, const struct irq_affinity_desc *affinity) argument
761 irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, irq_hw_number_t *hwirq, unsigned int *type) argument
796 irq_hw_number_t hwirq; local
940 __irq_resolve_mapping(struct irq_domain *domain, irq_hw_number_t hwirq, unsigned int *irq) argument
1089 irq_domain_alloc_descs(int virq, unsigned int cnt, irq_hw_number_t hwirq, int node, const struct irq_affinity_desc *affinity) argument
1192 irq_hw_number_t hwirq = data->hwirq; local
1369 irq_domain_set_hwirq_and_chip(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq, const struct irq_chip *chip, void *chip_data) argument
1398 irq_domain_set_info(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq, const struct irq_chip *chip, void *chip_data, irq_flow_handler_t handler, void *handler_data, const char *handler_name) argument
1908 irq_domain_set_info(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq, const struct irq_chip *chip, void *chip_data, irq_flow_handler_t handler, void *handler_data, const char *handler_name) argument
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/linux-master/drivers/misc/cxl/
H A Dirq.c174 irq_hw_number_t hwirq = irqd_to_hwirq(irq_get_irq_data(irq)); local
192 irq_off = hwirq - ctx->irqs.offset[r];
201 WARN(1, "Received AFU IRQ out of range for pe %i (virq %i hwirq %lx)\n",
202 ctx->pe, irq, hwirq);
206 trace_cxl_afu_irq(ctx, afu_irq, irq, hwirq);
207 pr_devel("Received AFU interrupt %i for pe: %i (virq %i hwirq %lx)\n",
208 afu_irq, ctx->pe, irq, hwirq);
224 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq, argument
231 virq = irq_create_mapping(NULL, hwirq);
238 cxl_ops->setup_irq(adapter, hwirq, vir
263 int hwirq, virq; local
359 irq_hw_number_t hwirq; local
404 irq_hw_number_t hwirq; local
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/linux-master/arch/powerpc/sysdev/
H A Dmpic.h10 extern void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq);
15 irq_hw_number_t hwirq)
14 mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq) argument
/linux-master/arch/arm/mach-orion5x/
H A Dirq.c34 unsigned int hwirq = 1 + __fls(stat); local
35 handle_IRQ(hwirq, regs);
/linux-master/arch/powerpc/platforms/embedded6xx/
H A Dhlwd-pic.c96 irq_hw_number_t hwirq)
125 unsigned int hwirq; local
131 hwirq = __hlwd_pic_get_irq(irq_domain);
132 if (hwirq)
133 generic_handle_domain_irq(irq_domain, hwirq);
191 unsigned int hwirq = __hlwd_pic_get_irq(hlwd_irq_host); local
192 return hwirq ? irq_linear_revmap(hlwd_irq_host, hwirq) : 0;
95 hlwd_pic_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hwirq) argument
/linux-master/drivers/pci/controller/
H A Dpcie-iproc-msi.c146 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) argument
148 return (hwirq % msi->nr_irqs);
152 unsigned long hwirq)
155 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
157 return hwirq_to_group(msi, hwirq) * sizeof(u32);
195 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) argument
197 return (hwirq % msi->nr_cpus);
201 unsigned long hwirq)
203 return (hwirq - hwirq_to_cpu(msi, hwirq));
151 iproc_msi_addr_offset(struct iproc_msi *msi, unsigned long hwirq) argument
200 hwirq_to_canonical_hwirq(struct iproc_msi *msi, unsigned long hwirq) argument
251 int hwirq, i; local
285 unsigned int hwirq; local
306 u32 hwirq; local
328 unsigned long hwirq; local
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/linux-master/arch/powerpc/include/asm/
H A Dmsi_bitmap.h23 void msi_bitmap_reserve_hwirq(struct msi_bitmap *bmp, unsigned int hwirq);
/linux-master/drivers/vfio/platform/
H A Dvfio_platform_irq.c25 disable_irq_nosync(irq_ctx->hwirq);
85 enable_irq(irq_ctx->hwirq);
161 disable_irq_nosync(irq_ctx->hwirq);
189 disable_irq(irq->hwirq);
210 enable_irq(irq->hwirq);
241 handler(irq->hwirq, irq);
247 handler(irq->hwirq, irq);
300 int hwirq = vdev->get_irq(vdev, i); local
303 if (hwirq < 0) {
312 if (irq_get_trigger_type(hwirq)
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/linux-master/arch/arm/mach-imx/
H A Davic.c52 static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type) argument
56 if (hwirq >= AVIC_NUM_IRQS)
59 if (hwirq < AVIC_NUM_IRQS / 2) {
60 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
61 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
63 hwirq -= AVIC_NUM_IRQS / 2;
64 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
65 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
86 int idx = d->hwirq >> 5;
92 u8 offs = d->hwirq < AVIC_NUM_IRQ
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