/linux-master/arch/parisc/kernel/ |
H A D | signal.c | 65 err |= __copy_from_user(regs->gr, sc->sc_gr, sizeof(regs->gr)); 72 DBG(2, "%s: r28 is %ld\n", __func__, regs->gr[28]); 81 unsigned long usp = (regs->gr[30] & ~(0x01UL)); 114 /* Good thing we saved the old gr[30], eh? */ 146 regs->gr[31] = regs->iaoq[0]; 190 err |= __put_user(regs->gr[31], &sc->sc_iaoq[0]); 191 err |= __put_user(regs->gr[31]+4, &sc->sc_iaoq[1]); 195 __func__, regs->gr[31], regs->gr[3 [all...] |
H A D | asm-offsets.c | 50 DEFINE(TASK_PT_PSW, offsetof(struct task_struct, thread.regs.gr[ 0])); 51 DEFINE(TASK_PT_GR1, offsetof(struct task_struct, thread.regs.gr[ 1])); 52 DEFINE(TASK_PT_GR2, offsetof(struct task_struct, thread.regs.gr[ 2])); 53 DEFINE(TASK_PT_GR3, offsetof(struct task_struct, thread.regs.gr[ 3])); 54 DEFINE(TASK_PT_GR4, offsetof(struct task_struct, thread.regs.gr[ 4])); 55 DEFINE(TASK_PT_GR5, offsetof(struct task_struct, thread.regs.gr[ 5])); 56 DEFINE(TASK_PT_GR6, offsetof(struct task_struct, thread.regs.gr[ 6])); 57 DEFINE(TASK_PT_GR7, offsetof(struct task_struct, thread.regs.gr[ 7])); 58 DEFINE(TASK_PT_GR8, offsetof(struct task_struct, thread.regs.gr[ 8])); 59 DEFINE(TASK_PT_GR9, offsetof(struct task_struct, thread.regs.gr[ [all...] |
H A D | signal32.c | 51 regs->gr[regn] = compat_reg; 54 regs->gr[regn] = ((u64)compat_regt << 32) | (u64)compat_reg; 55 DBG(3,"restore_sigcontext32: gr%02d = %#lx (%#x / %#x)\n", 56 regn, regs->gr[regn], compat_regt, compat_reg); 103 DBG(2,"restore_sigcontext32: r28 is %ld\n", regs->gr[28]); 133 compat_reg = (compat_uint_t)(regs->gr[31]); 140 compat_reg = (compat_uint_t)(regs->gr[31] >> 32); 145 compat_reg = (compat_uint_t)(regs->gr[31]+4); 150 compat_reg = (compat_uint_t)((regs->gr[31]+4) >> 32); 167 regs->gr[3 [all...] |
H A D | toc.c | 22 regs->gr[0] = (unsigned long)toc->cr[22]; 25 regs->gr[i] = (unsigned long)toc->gr[i]; 45 regs->gr[0] = toc->cr[22]; 48 regs->gr[i] = toc->gr[i];
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/linux-master/arch/parisc/include/asm/ |
H A D | ptrace.h | 20 #define user_stack_pointer(regs) ((regs)->gr[30]) 25 return regs->gr[28]; 40 #define kernel_stack_pointer(regs) ((regs)->gr[30])
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H A D | special_insns.h | 48 #define mtctl(gr, cr) \ 51 : "r" (gr), "i" (cr) : "memory")
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/linux-master/drivers/staging/media/atomisp/pci/isp/kernels/dp/dp_1.0/ |
H A D | ia_css_dp.host.c | 52 int gr = from->gr; local 66 uDIGIT_FITTING(gain * gr / r, 8, SH_CSS_DP_GAIN_SHIFT); 72 uDIGIT_FITTING(gain * gr / b, 8, SH_CSS_DP_GAIN_SHIFT); 74 uDIGIT_FITTING(gain * r / gr, 8, SH_CSS_DP_GAIN_SHIFT); 76 uDIGIT_FITTING(gain * b / gr, 8, SH_CSS_DP_GAIN_SHIFT);
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/linux-master/arch/parisc/include/uapi/asm/ |
H A D | ptrace.h | 25 unsigned long gr[32]; /* PSW is in gr[0] */ member in struct:pt_regs 52 unsigned long gr[32]; /* PSW is in gr[0] */ member in struct:user_regs_struct
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | ctxgf100.c | 998 nvkm_wr32(chan->gr->base.engine.subdev.device, addr, data); 1007 gf100_grctx_generate_r419cb8(struct gf100_gr *gr) argument 1009 struct nvkm_device *device = gr->base.engine.subdev.device; 1034 struct gf100_gr *gr = chan->gr; local 1035 const struct gf100_grctx_func *grctx = gr->func->grctx; 1042 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 1043 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { 1060 gf100_grctx_generate_attrib_cb_size(struct gf100_gr *gr) argument 1062 const struct gf100_grctx_func *grctx = gr 1068 gf100_grctx_generate_unkn(struct gf100_gr *gr) argument 1073 gf100_grctx_generate_r4060a8(struct gf100_gr *gr) argument 1093 gf100_grctx_generate_rop_mapping(struct gf100_gr *gr) argument 1139 gf100_grctx_generate_max_ways_evict(struct gf100_gr *gr) argument 1249 gf100_grctx_generate_alpha_beta_tables(struct gf100_gr *gr) argument 1285 gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc) argument 1293 gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 1303 gf100_grctx_generate_floorsweep(struct gf100_gr *gr) argument 1344 struct gf100_gr *gr = chan->gr; local 1436 gf100_grctx_generate(struct gf100_gr *gr, struct gf100_gr_chan *chan, struct nvkm_gpuobj *inst) argument [all...] |
H A D | ctxtu102.c | 25 tu102_grctx_generate_r419c0c(struct gf100_gr *gr) argument 27 struct nvkm_device *device = gr->base.engine.subdev.device; 34 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) argument 36 struct nvkm_device *device = gr->base.engine.subdev.device; 38 tpc = gv100_gr_nonpes_aware_tpc(gr, gpc, tpc);
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H A D | g84.c | 95 nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, argument 98 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 117 struct nv50_gr *gr = nv50_gr(base); local 118 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 127 spin_lock_irqsave(&gr->lock, flags); 158 nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, 160 nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1, 162 nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2, 173 spin_unlock_irqrestore(&gr->lock, flags);
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H A D | nv40.c | 34 nv40_gr_units(struct nvkm_gr *gr) argument 36 return nvkm_rd32(gr->engine.subdev.device, 0x1540); 78 struct nv40_gr *gr = chan->gr; local 79 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); 95 struct nv40_gr *gr = chan->gr; local 96 struct nvkm_subdev *subdev = &gr 151 struct nv40_gr *gr = nv40_gr(base); local 175 struct nv40_gr *gr = nv40_gr(base); local 234 struct nv40_gr *gr = nv40_gr(base); local 289 struct nv40_gr *gr = nv40_gr(base); local 434 struct nv40_gr *gr; local [all...] |
H A D | nv20.c | 20 struct nv20_gr *gr = chan->gr; local 23 nvkm_kmap(gr->ctxtab); 24 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); 25 nvkm_done(gr->ctxtab); 33 struct nv20_gr *gr = chan->gr; local 34 struct nvkm_device *device = gr->base.engine.subdev.device; 53 nvkm_kmap(gr->ctxtab); 54 nvkm_wo32(gr 78 struct nv20_gr *gr = nv20_gr(base); local 151 struct nv20_gr *gr = nv20_gr(base); local 182 struct nv20_gr *gr = nv20_gr(base); local 222 struct nv20_gr *gr = nv20_gr(base); local 231 struct nv20_gr *gr = nv20_gr(base); local 326 struct nv20_gr *gr = nv20_gr(base); local 335 struct nv20_gr *gr; local [all...] |
H A D | gm20b.c | 81 gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) argument 83 struct nvkm_device *device = gr->base.engine.subdev.device; 109 gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) argument 111 struct nvkm_device *device = gr->base.engine.subdev.device; 141 gm20b_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) argument 143 struct nvkm_subdev *subdev = &gr->base.engine.subdev; 146 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(subdev, &gr->fecs.falcon, 148 "gr/fecs_", ver, fwif->fecs); 153 if (nvkm_firmware_load_blob(subdev, "gr/", "gpccs_inst", ver, 154 &gr [all...] |
H A D | gk104.c | 391 gk104_gr_init_sked_hww_esr(struct gf100_gr *gr) argument 393 nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000); 397 gk104_gr_init_fecs_exceptions(struct gf100_gr *gr) argument 399 struct nvkm_device *device = gr->base.engine.subdev.device; 406 gk104_gr_init_rop_active_fbps(struct gf100_gr *gr) argument 408 struct nvkm_device *device = gr->base.engine.subdev.device; 415 gk104_gr_init_ppc_exceptions(struct gf100_gr *gr) argument 417 struct nvkm_device *device = gr->base.engine.subdev.device; 420 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { 421 for (ppc = 0; ppc < gr 430 gk104_gr_init_vsc_stream_master(struct gf100_gr *gr) argument [all...] |
H A D | nv20.h | 27 struct nv20_gr *gr; member in struct:nv20_gr_chan
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H A D | nv50.c | 33 nv50_gr_units(struct nvkm_gr *gr) argument 35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); 72 struct nv50_gr *gr = nv50_gr_chan(object)->gr; local 73 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, 77 nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); 92 struct nv50_gr *gr = nv50_gr(base); local 98 chan->gr = gr; 240 nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp) argument 282 nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) argument 325 nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, u32 ustatus_new, int display, const char *name) argument 395 nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, int chid, u64 inst, const char *name) argument 622 struct nv50_gr *gr = nv50_gr(base); local 681 struct nv50_gr *gr = nv50_gr(base); local 766 struct nv50_gr *gr; local [all...] |
H A D | nv04.c | 361 struct nv04_gr *gr; member in struct:nv04_gr_chan 1072 nv04_gr_channel(struct nv04_gr *gr) argument 1074 struct nvkm_device *device = gr->base.engine.subdev.device; 1078 if (chid < ARRAY_SIZE(gr->chan)) 1079 chan = gr->chan[chid]; 1087 struct nvkm_device *device = chan->gr->base.engine.subdev.device; 1102 struct nvkm_device *device = chan->gr->base.engine.subdev.device; 1114 nv04_gr_context_switch(struct nv04_gr *gr) argument 1116 struct nvkm_device *device = gr->base.engine.subdev.device; 1121 nv04_gr_idle(&gr 1151 struct nv04_gr *gr = chan->gr; local 1164 struct nv04_gr *gr = chan->gr; local 1187 struct nv04_gr *gr = nv04_gr(base); local 1211 nv04_gr_idle(struct nvkm_gr *gr) argument 1274 struct nv04_gr *gr = nv04_gr(base); local 1330 struct nv04_gr *gr = nv04_gr(base); local 1418 struct nv04_gr *gr; local [all...] |
/linux-master/drivers/clk/ |
H A D | clk-gemini.c | 224 struct gemini_reset *gr = to_gemini_reset(rcdev); local 227 return regmap_write(gr->map, 247 struct gemini_reset *gr = to_gemini_reset(rcdev); local 251 ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val); 271 struct gemini_reset *gr; local 281 gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL); 282 if (!gr) 296 gr->map = map; 297 gr [all...] |
/linux-master/arch/s390/include/asm/ |
H A D | fpu-insn-asm.h | 28 .macro GR_NUM opd gr 30 .ifc \gr,%r0 33 .ifc \gr,%r1 36 .ifc \gr,%r2 39 .ifc \gr,%r3 42 .ifc \gr,%r4 45 .ifc \gr,%r5 48 .ifc \gr,%r6 51 .ifc \gr,%r7 54 .ifc \gr, 286 .macro VLVG v, gr, disp, m variable 294 .macro VLVGB v, gr, index, base variable 295 VLVG \\v, \\gr, \\index, \\base, 0 variable 297 .macro VLVGH v, gr, index variable 298 VLVG \\v, \\gr, \\index, 1 variable 300 .macro VLVGF v, gr, index variable 301 VLVG \\v, \\gr, \\index, 2 variable 303 .macro VLVGG v, gr, index variable 304 VLVG \\v, \\gr, \\index, 3 variable 525 .macro VLL v, gr, disp, base variable 535 .macro VSTL v, gr, disp, base variable [all...] |
/linux-master/drivers/parisc/ |
H A D | power.c | 41 #define MTCPU(dr, gr) MFCPU_X(dr, gr, 0, 0x12) /* move value of gr to dr[dr] */ 42 #define MFCPU_C(dr, gr) MFCPU_X(dr, gr, 0, 0x30) /* for dr0 and dr8 only ! */ 43 #define MFCPU_T(dr, gr) MFCPU_X(dr, 0, gr, 0xa0) /* all dr except dr0 and dr8 */
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/linux-master/drivers/usb/dwc2/ |
H A D | core.c | 39 struct dwc2_gregs_backup *gr; local 44 gr = &hsotg->gr_backup; 46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); 47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); 48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); 49 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); 50 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 51 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 52 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 53 gr 71 struct dwc2_gregs_backup *gr; local 110 struct dwc2_gregs_backup *gr; local 150 struct dwc2_gregs_backup *gr; local [all...] |
/linux-master/arch/parisc/mm/ |
H A D | fault.c | 160 regs->gr[fault_error_reg] = -EFAULT; 168 regs->gr[treg] = 0; 182 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */ 478 regs->gr[breg] += regs->gr[xreg]; 480 regs->gr[0] |= PSW_N; 507 regs->gr[treg] = val; 508 regs->gr[0] |= PSW_N; 518 regs->gr[bre [all...] |
/linux-master/drivers/staging/media/atomisp/pci/isp/kernels/wb/wb_1.0/ |
H A D | ia_css_wb.host.c | 43 uDIGIT_FITTING(from->gr, 16 - from->integer_bits, 82 "config.integer_bits=%d, config.gr=%d, config.r=%d, config.b=%d, config.gb=%d\n", 84 config->gr, config->r,
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/linux-master/drivers/macintosh/ |
H A D | windfarm_pid.h | 32 s32 gd, gp, gr; /* PID gains */ member in struct:wf_pid_param 65 s32 gd, gp, gr; /* PID gains */ member in struct:wf_cpu_pid_param
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