/linux-master/drivers/clk/sunxi/ |
H A D | clk-a10-pll2.c | 45 struct clk_gate *gate; local 73 /* Setup the gate part of the PLL2 */ 74 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 75 if (!gate) 78 gate->reg = reg; 79 gate->bit_idx = SUN4I_PLL2_ENABLE; 80 gate->lock = &sun4i_a10_pll2_lock; 99 &gate->hw, &clk_gate_ops, 170 kfree(gate);
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H A D | clk-sun4i-display.c | 108 struct clk_gate *gate; local 138 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 139 if (!gate) 142 gate->reg = reg; 143 gate->bit_idx = data->offset_en; 144 gate->lock = &sun4i_a10_display_lock; 162 &gate->hw, &clk_gate_ops, 213 kfree(gate);
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H A D | clk-factors.c | 183 struct clk_gate *gate = NULL; local 214 /* Add a gate if this factor clock can be gated */ 216 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 217 if (!gate) 220 factors->gate = gate; 222 /* set up gate properties */ 223 gate->reg = reg; 224 gate->bit_idx = data->enable; 225 gate [all...] |
/linux-master/drivers/staging/sm750fb/ |
H A D | ddk750_power.h | 19 void sm750_set_current_gate(unsigned int gate);
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/linux-master/drivers/clk/bcm/ |
H A D | clk-kona.h | 46 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 47 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 48 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 49 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) 50 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GAT 384 struct bcm_clk_gate gate; member in struct:peri_clk_data [all...] |
H A D | clk-kona-setup.c | 73 struct bcm_clk_gate *gate; local 99 gate = &peri->gate; 101 if (gate_exists(gate)) { 102 if (gate->offset > limit) { 103 pr_err("%s: bad gate offset for %s (%u > %u)\n", 104 __func__, name, gate->offset, limit); 117 pr_err("%s: hysteresis but no gate for %s\n", __func__, name); 242 * have an enable bit. And a gate that can be hardware or software 245 static bool gate_valid(struct bcm_clk_gate *gate, cons argument 396 struct bcm_clk_gate *gate; local [all...] |
/linux-master/drivers/clk/rockchip/ |
H A D | clk-half-divider.c | 171 struct clk_gate *gate = NULL; local 191 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 192 if (!gate) 195 gate->flags = gate_flags; 196 gate->reg = base + gate_offset; 197 gate->bit_idx = gate_shift; 198 gate->lock = lock; 218 gate ? &gate [all...] |
/linux-master/include/net/nfc/ |
H A D | hci.h | 32 int (*target_from_gate) (struct nfc_hci_dev *hdev, u8 gate, 34 int (*complete_target_discovered) (struct nfc_hci_dev *hdev, u8 gate, 64 u8 gate; member in struct:nfc_hci_gate 69 u8 gate; member in struct:nfc_hci_pipe 244 /* Reader Application gate events */ 259 int nfc_hci_disconnect_gate(struct nfc_hci_dev *hdev, u8 gate); 261 int nfc_hci_get_param(struct nfc_hci_dev *hdev, u8 gate, u8 idx, 263 int nfc_hci_set_param(struct nfc_hci_dev *hdev, u8 gate, u8 idx, 265 int nfc_hci_send_cmd(struct nfc_hci_dev *hdev, u8 gate, u8 cmd, 267 int nfc_hci_send_cmd_async(struct nfc_hci_dev *hdev, u8 gate, u [all...] |
/linux-master/drivers/clk/tegra/ |
H A D | clk-sdmmc-mux.c | 170 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; 181 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; 192 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; 201 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; 261 sdmmc_mux->gate.clk_base = clk_base; 262 sdmmc_mux->gate.regs = bank; 263 sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt; 264 sdmmc_mux->gate.clk_num = clk_num; 265 sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB; 275 sdmmc_mux->gate [all...] |
/linux-master/drivers/clk/ti/ |
H A D | gate.c | 3 * OMAP gate clock support 170 struct clk_hw_omap *gate; local 172 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 173 if (!gate) 176 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg)) 179 gate->enable_bit = gate->enable_reg.bit; 180 gate->ops = hw_ops; 182 if (!ti_clk_add_component(node, &gate [all...] |
/linux-master/drivers/clk/meson/ |
H A D | clk-regmap.c | 13 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); local 14 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; 18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), 19 set ? BIT(gate->bit_idx) : 0); 35 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); local 38 regmap_read(clk->map, gate->offset, &val); 39 if (gate->flags & CLK_GATE_SET_TO_DISABLE) 40 val ^= BIT(gate->bit_idx); 42 val &= BIT(gate [all...] |
/linux-master/drivers/clk/pistachio/ |
H A D | clk.c | 58 struct pistachio_gate *gate, 65 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, 67 p->base + gate[i].reg, gate[i].shift, 69 p->clk_data.clks[gate[i].id] = clk; 57 pistachio_clk_register_gate(struct pistachio_clk_provider *p, struct pistachio_gate *gate, unsigned int num) argument
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/linux-master/drivers/clk/davinci/ |
H A D | da8xx-cfgchip.c | 93 struct da8xx_cfgchip_gate_clk *gate; local 103 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); 104 if (!gate) 116 gate->hw.init = &init; 117 gate->regmap = regmap; 118 gate->reg = info->cfgchip; 119 gate->mask = info->bit; 121 ret = devm_clk_hw_register(dev, &gate->hw); 125 return gate; 137 struct da8xx_cfgchip_gate_clk *gate; local 160 struct da8xx_cfgchip_gate_clk *gate; local 172 struct da8xx_cfgchip_gate_clk *gate; local [all...] |
/linux-master/sound/soc/mediatek/mt8195/ |
H A D | mt8195-audsys-clk.c | 189 const struct afe_gate *gate = &aud_clks[i]; local 191 clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, 192 gate->flags, afe->base_addr + gate->reg, 193 gate->bit, gate->cg_flags, NULL); 197 gate->name, PTR_ERR(clk)); 207 cl->con_id = gate->name;
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/linux-master/sound/soc/mediatek/mt8188/ |
H A D | mt8188-audsys-clk.c | 179 const struct afe_gate *gate = &aud_clks[i]; local 181 clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, 182 gate->flags, afe->base_addr + gate->reg, 183 gate->bit, gate->cg_flags, NULL); 187 gate->name, PTR_ERR(clk)); 197 cl->con_id = gate->name;
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/linux-master/drivers/clk/imx/ |
H A D | clk-composite-8m.c | 216 struct clk_gate *gate = NULL; local 259 /* skip registering the gate ops if M4 is enabled */ 261 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 262 if (!gate) 265 gate_hw = &gate->hw; 266 gate->reg = reg; 267 gate->bit_idx = PCG_CGC_SHIFT; 268 gate->lock = &imx_ccm_lock; 280 kfree(gate); [all...] |
/linux-master/drivers/clk/sophgo/ |
H A D | clk-cv18xx-ip.h | 13 struct cv1800_clk_regbit gate; member in struct:cv1800_clk_gate 26 struct cv1800_clk_regbit gate; member in struct:cv1800_clk_div 37 struct cv1800_clk_regbit gate; member in struct:cv1800_clk_mux 49 struct cv1800_clk_regbit gate; member in struct:cv1800_clk_mmux 74 .gate = CV1800_CLK_BIT(_gate_reg, _gate_shift), \ 83 .gate = CV1800_CLK_BIT(_gate_reg, \ 98 .gate = CV1800_CLK_BIT(_gate_reg, \ 154 .gate = CV1800_CLK_BIT(_gate_reg, \ 203 .gate = CV1800_CLK_BIT(_gate_reg, _gate_shift),\
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/linux-master/drivers/clk/ |
H A D | clk-stm32f4.c | 369 * have gate bits associated with them. Its combined hweight is 71. 514 struct clk_gate gate; member in struct:stm32f4_pll 521 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate) 607 struct clk_gate *gate = to_clk_gate(hw); local 608 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 618 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx)); 633 struct clk_gate *gate = to_clk_gate(hw); local 634 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 645 struct clk_gate *gate = to_clk_gate(hw); local 646 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 662 struct clk_gate *gate = to_clk_gate(hw); local 909 struct clk_gate gate; member in struct:stm32_rgate 917 struct clk_gate *gate = to_clk_gate(hw); local 1059 struct clk_gate *gate; local 1630 struct clk_gate *gate = NULL; local [all...] |
H A D | clk-stm32h7.c | 151 struct clk_gate gate; member in struct:stm32_ready_gate 156 gate) 162 struct clk_gate *gate = to_clk_gate(hw); local 163 struct stm32_ready_gate *rgate = to_ready_gate_clk(gate); 178 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy)); 190 struct clk_gate *gate = to_clk_gate(hw); local 191 struct stm32_ready_gate *rgate = to_ready_gate_clk(gate); 201 bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy)); 236 rgate->gate.lock = lock; 237 rgate->gate 263 struct gate_cfg *gate; member in struct:composite_clk_cfg 283 struct composite_clk_gcfg_t *gate; member in struct:composite_clk_gcfg 335 struct clk_gate *gate; local 365 struct clk_gate *gate = NULL; local [all...] |
/linux-master/drivers/clk/x86/ |
H A D | clk-cgu.c | 259 struct lgm_clk_gate *gate = to_lgm_clk_gate(hw); local 262 reg = GATE_HW_REG_EN(gate->reg); 263 lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); 270 struct lgm_clk_gate *gate = to_lgm_clk_gate(hw); local 273 reg = GATE_HW_REG_DIS(gate->reg); 274 lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); 279 struct lgm_clk_gate *gate = to_lgm_clk_gate(hw); local 282 reg = GATE_HW_REG_STAT(gate 303 struct lgm_clk_gate *gate; local [all...] |
/linux-master/drivers/clk/uniphier/ |
H A D | Makefile | 7 obj-y += clk-uniphier-gate.o
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/linux-master/drivers/clk/nxp/ |
H A D | clk-lpc18xx-ccu.c | 40 struct clk_gate gate; member in struct:lpc18xx_clk_branch 136 struct clk_gate *gate = to_clk_gate(hw); local 143 val = readl(gate->reg); 156 writel(val, gate->reg); 161 writel(val, gate->reg); 224 branch->gate.reg = branch->offset + reg_base; 225 branch->gate.bit_idx = 0; 230 &branch->gate.hw, &lpc18xx_ccu_gate_ops, 0);
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/linux-master/drivers/clk/sprd/ |
H A D | Makefile | 5 clk-sprd-y += gate.o
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/linux-master/drivers/clk/mmp/ |
H A D | Makefile | 6 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
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/linux-master/drivers/clk/sunxi-ng/ |
H A D | ccu_gate.h | 121 void ccu_gate_helper_disable(struct ccu_common *common, u32 gate); 122 int ccu_gate_helper_enable(struct ccu_common *common, u32 gate); 123 int ccu_gate_helper_is_enabled(struct ccu_common *common, u32 gate);
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