Searched refs:engine (Results 251 - 275 of 539) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_gt.h93 #define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
94 intel_gt_needs_wa_16018031267(engine->gt) && \
95 engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
190 for_each_if ((engine__) = (gt__)->engine[(id__)])
196 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv40.c31 #include <engine/fifo.h>
36 return nvkm_rd32(gr->engine.subdev.device, 0x1540);
47 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align,
79 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
96 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
134 spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
136 spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
162 spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
164 spin_unlock_irqrestore(&chan->gr->base.engine
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H A Dgp102.c32 struct nvkm_device *device = gr->base.engine.subdev.device;
47 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
88 struct nvkm_device *device = gr->base.engine.subdev.device;
H A Dnv44.c28 #include <engine/fifo.h>
34 struct nvkm_device *device = gr->base.engine.subdev.device;
/linux-master/drivers/dma/sh/
H A Drz-dmac.c93 struct dma_device engine; member in struct:rz_dmac
105 #define to_rz_dmac(d) container_of(d, struct rz_dmac, engine)
413 * DMA engine operations
815 vchan_init(&channel->vc, &dmac->engine);
845 struct dma_device *engine; local
891 INIT_LIST_HEAD(&dmac->engine.channels);
921 /* Register the DMA engine device. */
922 engine = &dmac->engine;
923 dma_cap_set(DMA_SLAVE, engine
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H A Dusb-dmac.c91 * @engine: base DMA engine object
98 struct dma_device engine; member in struct:usb_dmac
106 #define to_usb_dmac(d) container_of(d, struct usb_dmac, engine)
378 * DMA engine operations
739 vchan_init(&uchan->vc, &dmac->engine);
769 struct dma_device *engine; local
811 INIT_LIST_HEAD(&dmac->engine.channels);
826 * Register the DMA engine device.
830 engine
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/linux-master/drivers/crypto/amlogic/
H A Damlogic-gxl-cipher.c261 int meson_handle_cipher_request(struct crypto_engine *engine, void *areq) argument
268 crypto_finalize_skcipher_request(engine, breq, err);
279 struct crypto_engine *engine; local
286 engine = op->mc->chanlist[e].engine;
289 return crypto_transfer_skcipher_request_to_engine(engine, areq);
297 struct crypto_engine *engine; local
304 engine = op->mc->chanlist[e].engine;
307 return crypto_transfer_skcipher_request_to_engine(engine, are
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/linux-master/drivers/crypto/rockchip/
H A Drk3288_crypto_ahash.c209 struct crypto_engine *engine; local
220 engine = dev->engine;
222 return crypto_transfer_hash_request_to_engine(engine, req);
233 static int rk_hash_prepare(struct crypto_engine *engine, void *breq) argument
249 static void rk_hash_unprepare(struct crypto_engine *engine, void *breq) argument
258 static int rk_hash_run(struct crypto_engine *engine, void *breq) argument
275 err = rk_hash_prepare(engine, breq);
335 rk_hash_unprepare(engine, breq);
338 crypto_finalize_hash_request(engine, bre
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/linux-master/drivers/gpu/drm/i915/
H A Di915_query.c105 struct intel_engine_cs *engine; local
113 engine = intel_engine_lookup_user(i915, (u8)classinstance.engine_class,
116 if (!engine)
119 if (engine->class != RENDER_CLASS)
122 sseu = &engine->gt->info.sseu;
137 struct intel_engine_cs *engine; local
143 for_each_uabi_engine(engine, i915)
158 for_each_uabi_engine(engine, i915) {
159 info.engine.engine_class = engine
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/linux-master/drivers/accel/ivpu/
H A Divpu_job.c31 static struct ivpu_cmdq *ivpu_cmdq_alloc(struct ivpu_file_priv *file_priv, u16 engine) argument
58 jobq_header->engine_idx = engine;
82 static struct ivpu_cmdq *ivpu_cmdq_acquire(struct ivpu_file_priv *file_priv, u16 engine) argument
85 struct ivpu_cmdq *cmdq = file_priv->cmdq[engine];
91 cmdq = ivpu_cmdq_alloc(file_priv, engine);
94 file_priv->cmdq[engine] = cmdq;
110 static void ivpu_cmdq_release_locked(struct ivpu_file_priv *file_priv, u16 engine) argument
112 struct ivpu_cmdq *cmdq = file_priv->cmdq[engine];
117 file_priv->cmdq[engine] = NULL;
141 static void ivpu_cmdq_reset_locked(struct ivpu_file_priv *file_priv, u16 engine) argument
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/linux-master/drivers/gpu/drm/i915/selftests/
H A Di915_gem_evict.c381 struct intel_engine_cs *engine; local
449 for_each_engine(engine, gt, id) {
459 ce = intel_context_create(engine);
473 engine->name,
496 count, engine->name);
504 engine->name);
509 err = intel_gt_wait_for_idle(engine->gt, HZ * 3);
511 gt_err(engine->gt, "Failed to idle GT (on %s)",
512 engine->name);
/linux-master/drivers/crypto/tegra/
H A Dtegra-se-main.c13 #include <crypto/engine.h>
303 se->engine = crypto_engine_alloc_init(dev, 0);
304 if (!se->engine)
305 return dev_err_probe(dev, -ENOMEM, "failed to init crypto engine\n");
307 ret = crypto_engine_start(se->engine);
309 crypto_engine_exit(se->engine);
310 return dev_err_probe(dev, ret, "failed to start crypto engine\n");
315 crypto_engine_stop(se->engine);
316 crypto_engine_exit(se->engine);
327 crypto_engine_stop(se->engine);
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dnv40.c41 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
114 struct nvkm_instmem *imem = fifo->engine.subdev.device->imem;
128 struct nvkm_device *device = fifo->engine.subdev.device;
133 switch (engn->engine->subdev.type) {
183 struct nvkm_device *device = fifo->engine.subdev.device;
H A Dgm107.c94 .engine = gm107_fifo_mmu_fault_engine,
103 struct nvkm_device *device = fifo->engine.subdev.device;
113 info.engine = unit;
H A Dg84.c37 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device;
45 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device;
108 struct nvkm_subdev *subdev = &chan->cgrp->runl->fifo->engine.subdev;
113 switch (engn->engine->subdev.type) {
168 nvkm_mask(fifo->engine.subdev.device, 0x002140, 0x40000000, 0x00000000);
179 nvkm_mask(fifo->engine.subdev.device, 0x002140, 0x40000000, 0x40000000);
/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_uc.c104 * its engine mask is set, so we use the device info engine mask for it.
132 * engine mask
214 struct intel_engine_cs *engine = gt->engine[GSC0]; local
226 ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
295 if (!gsc_uc_to_gt(gsc)->engine[GSC0]->default_state)
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgm200.c36 struct nvkm_device *device = sor->disp->engine.subdev.device;
74 struct nvkm_device *device = ior->disp->engine.subdev.device;
101 struct nvkm_device *device = outp->disp->engine.subdev.device;
118 struct nvkm_device *device = outp->disp->engine.subdev.device;
159 struct nvkm_device *device = disp->engine.subdev.device;
H A Dgp102.c36 struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
105 struct nvkm_subdev *subdev = &chan->disp->engine.subdev;
150 struct nvkm_subdev *subdev = &disp->engine.subdev;
H A Dga102.c35 struct nvkm_device *device = sor->disp->engine.subdev.device;
88 struct nvkm_device *device = sor->disp->engine.subdev.device;
118 struct nvkm_device *device = disp->engine.subdev.device;
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dga102.c62 struct nvkm_device *device = sec2->engine.subdev.device;
106 &sec2->engine.subdev,
180 return nvkm_acr_lsfw_load_sig_image_desc_v2(&sec2->engine.subdev, &sec2->falcon,
/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Dmock_context.c111 live_context_for_engine(struct intel_engine_cs *engine, struct file *file) argument
122 ctx = live_context(engine->i915, file);
128 ce = intel_context_create(engine);
H A Di915_gem_client_blt.c154 struct intel_gt *gt = t->ce->engine->gt;
162 *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
298 struct drm_i915_private *i915 = t->ce->engine->i915;
511 err = rq->engine->emit_bb_start(rq,
532 tiled_blits_create(struct intel_engine_cs *engine, struct rnd_state *prng) argument
543 t->ce = intel_context_create(engine);
658 static int __igt_client_tiled_blits(struct intel_engine_cs *engine, argument
664 t = tiled_blits_create(engine, prng);
715 struct intel_engine_cs *engine; local
718 engine
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/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c156 struct intel_engine_cs *engine; local
158 engine = intel_engine_lookup_user(ctx->i915,
161 if (!engine)
164 idx = engine->legacy_idx;
233 * If the per-engine reset fails, all hope is lost! We resort
235 * if the engine could not reset, the full reset does not fare
238 * However, if we cannot reset an engine by itself, we cannot
470 set->engines[idx].engine = siblings[0];
510 "Invalid index for virtual engine: %d >= %d\n",
517 drm_dbg(&i915->drm, "Invalid engine a
769 struct intel_engine_cs *engine; local
1118 struct intel_engine_cs *engine; local
1328 __reset_context(struct i915_gem_context *ctx, struct intel_engine_cs *engine) argument
1335 __cancel_engine(struct intel_engine_cs *engine) argument
1356 struct intel_engine_cs *engine = NULL; local
1406 struct intel_engine_cs *engine; local
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/dma/
H A Dusernv04.c45 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
84 struct nvkm_device *device = dma->engine.subdev.device;
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dexeclist.h175 const struct intel_engine_cs *engine; member in struct:intel_vgpu_execlist
183 const struct intel_engine_cs *engine);

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