Searched refs:clear (Results 251 - 275 of 537) sorted by relevance

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/linux-master/drivers/video/fbdev/core/
H A Dtileblit.c137 ops->clear = tile_clear;
/linux-master/include/linux/
H A Dserdev.h261 static inline int serdev_device_set_tiocm(struct serdev_device *serdev, int set, int clear) argument
H A Dtty_driver.h269 * unsigned int set, unsigned int clear)``
272 * First, @clear bits should be cleared, then @set bits set.
388 unsigned int set, unsigned int clear);
/linux-master/drivers/crypto/starfive/
H A Djh7110-cryp.h155 u32 clear :1; member in struct:starfive_alg_cr::__anon249
/linux-master/drivers/regulator/
H A Dda9121-regulator.c161 * and status polled until clear again and IRQ is reenabled.
623 int clear[3] = {0}; local
648 clear[reg_idx] |= item->mask_bit;
654 if (clear[i]) {
656 unsigned int mbit = clear[i];
755 /* clear the events */
/linux-master/tools/arch/arm64/include/asm/
H A Dsysreg.h805 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
808 #define sysreg_clear_set(sysreg, clear, set) do { \
810 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
815 #define sysreg_clear_set_s(sysreg, clear, set) do { \
817 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
/linux-master/arch/powerpc/sysdev/
H A Ddart_iommu.c70 * control register and wait for it to clear.
73 * set. If so, clear it and set it again.
326 .clear = dart_free,
/linux-master/drivers/cxl/core/
H A Dmemdev.c336 struct cxl_mbox_clear_poison clear; local
362 * address to clear. This driver uses zeroes as write-data.
364 clear = (struct cxl_mbox_clear_poison) {
370 .size_in = sizeof(clear),
371 .payload_in = &clear,
381 "poison clear dpa:%#llx region: %s\n", dpa,
/linux-master/include/drm/ttm/
H A Dttm_bo.h415 void ttm_move_memcpy(bool clear, u32 num_pages,
/linux-master/arch/arm/mm/
H A Dproc-sa110.S191 crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
H A Dproc-arm720.S165 crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
/linux-master/drivers/pci/msi/
H A Dmsi.c114 void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set) argument
123 desc->pci.msi_mask &= ~clear;
546 static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) argument
551 ctrl &= ~clear;
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_svm.h173 bool clear);
/linux-master/drivers/tty/
H A Dmxser.c297 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, argument
306 efr &= ~clear;
362 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) argument
364 __mxser_must_set_EFR(baseio, clear, set, true);
792 * And clear the interrupt registers again for luck.
841 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
849 /* clear Rx/Tx FIFO's */
1121 unsigned int set, unsigned int clear)
1136 if (clear & TIOCM_RTS)
1138 if (clear
1120 mxser_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) argument
[all...]
/linux-master/fs/btrfs/
H A Dsysfs.c148 u64 set, clear; local
152 clear = BTRFS_FEATURE_COMPAT_SAFE_CLEAR;
156 clear = BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR;
160 clear = BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR;
170 if (clear & fa->feature_bit)
198 u64 features, set, clear; local
215 clear = BTRFS_FEATURE_COMPAT_SAFE_CLEAR;
218 clear = BTRFS_FEATURE_COMPAT_RO_SAFE_CLEAR;
221 clear = BTRFS_FEATURE_INCOMPAT_SAFE_CLEAR;
232 (!val && !(clear
[all...]
H A Dextent-io-tree.c563 * Utility function to clear some bits in an extent state struct. It will
634 int clear = 0; local
651 clear = 1;
668 if (clear) {
675 if (clear)
680 if (clear)
711 * If the extent we found is inside our range, we clear the desired bit
735 * We need to split the extent, and clear the bit on the first half.
780 * Wait for one or more bits to clear on a range in the state tree.
839 /* This state is no longer useful, clear i
[all...]
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_workarounds.c187 "Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
218 u32 clear, u32 set, u32 read_mask, bool masked_reg)
222 .clr = clear,
232 u32 clear, u32 set, u32 read_mask, bool masked_reg)
236 .clr = clear,
247 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) argument
249 wa_add(wal, reg, clear, set, clear | set, false);
253 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) argument
255 wa_mcr_add(wal, reg, clear, se
217 wa_add(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set, u32 read_mask, bool masked_reg) argument
231 wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set, u32 read_mask, bool masked_reg) argument
[all...]
/linux-master/drivers/infiniband/hw/mlx4/
H A Dmcg.c1176 int clear; local
1183 clear = 1;
1187 clear = cancel_delayed_work(&group->timeout_work);
1188 pend = !clear;
1191 if (clear) {
1245 /* clear pending requests of this VF */
/linux-master/arch/sparc/mm/
H A Dsrmmu.c1082 volatile unsigned long clear; local
1099 clear = srmmu_get_faddr();
1100 clear = srmmu_get_fstatus();
1268 volatile unsigned long clear; local
1272 clear = srmmu_get_fstatus();
/linux-master/drivers/usb/serial/
H A Dftdi_sio.c1204 #define clear_mctrl(port, clear) update_mctrl((port), 0, (clear))
1207 unsigned int clear)
1214 if (((set | clear) & (TIOCM_DTR | TIOCM_RTS)) == 0) {
1219 clear &= ~set; /* 'set' takes precedence over 'clear' */
1221 if (clear & TIOCM_DTR)
1223 if (clear & TIOCM_RTS)
1238 (set & TIOCM_DTR) ? "HIGH" : (clear & TIOCM_DTR) ? "LOW" : "unchanged",
1239 (set & TIOCM_RTS) ? "HIGH" : (clear
1206 update_mctrl(struct usb_serial_port *port, unsigned int set, unsigned int clear) argument
2848 ftdi_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s100 clear b32 $r0
161 // and clear bit 30, then write back
231 clear b32 $r3
415 clear b32 $r3
/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_vcap_impl.c1336 bool clear = (cmd == VCAP_CMD_INITIALIZE); local
1345 VCAP_SUPER_CTRL_CLEAR_CACHE_SET(clear) |
1355 bool clear = (cmd == VCAP_CMD_INITIALIZE); local
1364 VCAP_ES0_CTRL_CLEAR_CACHE_SET(clear) |
1374 bool clear = (cmd == VCAP_CMD_INITIALIZE); local
1383 VCAP_ES2_CTRL_CLEAR_CACHE_SET(clear) |
/linux-master/arch/sparc/kernel/
H A Dentry.S282 st %o2, [%o1 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x70000000
327 st %o2, [%o5 + 0x04] ! sun4m_irq_percpu[cpu]->clear=0x80000000
724 andn %l0, %l5, %l0 ! clear ICC bits in %psr
725 and %l4, %l5, %l4 ! clear non-ICC bits in user value
1013 /* System call success, clear Carry condition code. */
1235 rd %psr, %o5 ! must clear interrupts
1252 st %g0, [%g6 + TI_UWINMASK] ! clear uwinmask
/linux-master/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dcn10k_macsec.c511 * if VLAN tag needs to be sent in clear text.
750 enum mcs_direction dir, bool clear)
769 if (!clear)
805 enum mcs_direction dir, bool clear)
824 if (!clear)
860 enum mcs_direction dir, bool clear)
879 if (!clear)
748 cn10k_mcs_sa_stats(struct otx2_nic *pfvf, u8 hw_sa_id, struct mcs_sa_stats *rsp_p, enum mcs_direction dir, bool clear) argument
803 cn10k_mcs_sc_stats(struct otx2_nic *pfvf, u8 hw_sc_id, struct mcs_sc_stats *rsp_p, enum mcs_direction dir, bool clear) argument
858 cn10k_mcs_secy_stats(struct otx2_nic *pfvf, u8 hw_secy_id, struct mcs_secy_stats *rsp_p, enum mcs_direction dir, bool clear) argument
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c158 /* Set and clear the OOB for DCVS to trigger the GMU */
258 int set, ack, set_new, ack_new, clear, clear_new; member in struct:a6xx_gmu_oob_bits
272 .clear = 24,
282 .clear = 25,
290 .clear = 30,
297 .clear = 31,
357 bit = a6xx_gmu_oob_bits[state].clear;

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