Searched refs:ce (Results 101 - 125 of 212) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_breadcrumbs.h48 void intel_context_remove_breadcrumbs(struct intel_context *ce,
H A Dintel_renderstate.c143 struct intel_context *ce)
145 struct intel_engine_cs *engine = ce->engine;
169 err = intel_context_pin_ww(ce, &so->ww);
194 intel_context_unpin(ce);
240 struct intel_context *ce)
247 intel_context_unpin(ce);
142 intel_renderstate_init(struct intel_renderstate *so, struct intel_context *ce) argument
239 intel_renderstate_fini(struct intel_renderstate *so, struct intel_context *ce) argument
H A Dselftest_reset.c59 struct intel_context *ce; local
68 ce = intel_context_create(engine);
69 if (IS_ERR(ce)) {
70 err = PTR_ERR(ce);
73 rq = igt_spinner_create_request(&spin, ce, MI_ARB_CHECK);
74 intel_context_put(ce);
/linux-master/drivers/net/wireless/ath/ath12k/
H A DMakefile16 ce.o \
H A Dce.c233 lockdep_assert_held(&ab->ce.ce_lock);
281 spin_lock_bh(&ab->ce.ce_lock);
295 ath12k_warn(ab, "failed to dma map ce rx buf\n");
315 spin_unlock_bh(&ab->ce.ce_lock);
329 spin_lock_bh(&ab->ce.ce_lock);
364 spin_unlock_bh(&ab->ce.ce_lock);
395 ath12k_dbg(ab, ATH12K_DBG_AHB, "rx ce pipe %d len %d\n",
418 spin_lock_bh(&ab->ce.ce_lock);
445 spin_unlock_bh(&ab->ce.ce_lock);
582 struct ath12k_ce_pipe *pipe = &ab->ce
[all...]
/linux-master/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c293 struct intel_context *ce; local
309 ce = intel_context_create(stream->engine);
310 if (IS_ERR(ce)) {
311 err = PTR_ERR(ce);
315 /* Poison the ce->vm so we detect writes not to the GGTT gt->scratch */
316 scratch = __px_vaddr(ce->vm->scratch[0]);
319 rq = intel_context_create_request(ce);
414 intel_context_put(ce);
/linux-master/drivers/net/ethernet/chelsio/cxgb/
H A Dsge.c504 struct freelQ_ce *ce = &q->centries[cidx]; local
506 dma_unmap_single(&pdev->dev, dma_unmap_addr(ce, dma_addr),
507 dma_unmap_len(ce, dma_len), DMA_FROM_DEVICE);
508 dev_kfree_skb(ce->skb);
509 ce->skb = NULL;
614 struct cmdQ_ce *ce; local
619 ce = &q->centries[cidx];
621 if (likely(dma_unmap_len(ce, dma_len))) {
623 dma_unmap_addr(ce, dma_addr),
624 dma_unmap_len(ce, dma_le
824 struct freelQ_ce *ce = &q->centries[q->pidx]; local
1043 const struct freelQ_ce *ce = &fl->centries[fl->cidx]; local
1092 struct freelQ_ce *ce = &fl->centries[fl->cidx]; local
1160 write_large_page_tx_descs(unsigned int pidx, struct cmdQ_e **e, struct cmdQ_ce **ce, unsigned int *gen, dma_addr_t *desc_mapping, unsigned int *desc_len, unsigned int nfrags, struct cmdQ *q) argument
1207 struct cmdQ_ce *ce; local
[all...]
/linux-master/arch/sparc/kernel/
H A Dsun4m_smp.c246 struct clock_event_device *ce; local
251 ce = &per_cpu(sparc32_clockevent, cpu);
253 if (clockevent_state_periodic(ce))
259 ce->event_handler(ce);
H A Dsun4d_smp.c370 struct clock_event_device *ce; local
386 ce = &per_cpu(sparc32_clockevent, cpu);
389 ce->event_handler(ce);
/linux-master/drivers/soc/qcom/
H A Dramp_controller.c93 * @ce: Configuration entry to update
97 static int rc_set_cfg_update(struct qcom_ramp_controller *qrc, u8 ce) argument
105 ack = FIELD_PREP(RC_CFG_ACK, BIT(ce));
108 ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce);
143 * @ce: Configuration SID
150 u16 ce, u8 nsids)
167 ret = rc_set_cfg_update(qrc, (u8)ce - i);
148 rc_write_cfg(struct qcom_ramp_controller *qrc, const struct reg_sequence *seq, u16 ce, u8 nsids) argument
/linux-master/drivers/crypto/gemini/
H A Dsl3516-ce.h3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
296 * @ce: pointer to the private data of driver handling this TFM
302 struct sl3516_ce_dev *ce; member in struct:sl3516_ce_cipher_tfm_ctx
310 * @ce: pointer to the sl3516_ce_dev structure associated with
320 struct sl3516_ce_dev *ce; member in struct:sl3516_ce_alg_template
338 int sl3516_ce_run_task(struct sl3516_ce_dev *ce,
341 int sl3516_ce_rng_register(struct sl3516_ce_dev *ce);
342 void sl3516_ce_rng_unregister(struct sl3516_ce_dev *ce);
/linux-master/drivers/gpu/drm/i915/
H A Di915_perf.c1282 struct intel_context *ce; local
1286 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1287 if (ce->engine != stream->engine) /* first match! */
1304 err = intel_context_pin_ww(ce, &ww);
1315 stream->pinned_ctx = ce;
1343 __read_reg(struct intel_context *ce, i915_reg_t reg, u32 ggtt_offset) argument
1348 rq = i915_request_create(ce);
1366 gen12_guc_sw_ctx_id(struct intel_context *ce, u32 *ctx_id) argument
1372 scratch = __vm_create_scratch_for_read_pinned(&ce->engine->gt->ggtt->vm, 4);
1380 err = __read_reg(ce, RING_EXECLIST_STATUS_H
1459 oa_context_image_offset(struct intel_context *ce, u32 reg) argument
1486 set_oa_ctx_ctrl_offset(struct intel_context *ce) argument
1524 struct intel_context *ce; local
1614 struct intel_context *ce; local
2302 emit_oa_config(struct i915_perf_stream *stream, struct i915_oa_config *oa_config, struct intel_context *ce, struct i915_active *active) argument
2444 gen8_update_reg_state_unlocked(const struct intel_context *ce, const struct i915_perf_stream *stream) argument
2479 gen8_store_flex(struct i915_request *rq, struct intel_context *ce, const struct flex *flex, unsigned int count) argument
2504 gen8_load_flex(struct i915_request *rq, struct intel_context *ce, const struct flex *flex, unsigned int count) argument
2528 gen8_modify_context(struct intel_context *ce, const struct flex *flex, unsigned int count) argument
2548 gen8_modify_self(struct intel_context *ce, const struct flex *flex, unsigned int count, struct i915_active *active) argument
2581 struct intel_context *ce; local
2610 struct intel_context *ce = stream->pinned_ctx; local
2736 struct intel_context *ce = engine->kernel_context; local
3426 i915_oa_init_reg_state(const struct intel_context *ce, const struct intel_engine_cs *engine) argument
[all...]
H A Di915_perf.h36 void i915_oa_init_reg_state(const struct intel_context *ce,
/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2480 static struct i915_request *eb_throttle(struct i915_execbuffer *eb, struct intel_context *ce) argument
2482 struct intel_ring *ring = ce->ring;
2483 struct intel_timeline *tl = ce->timeline;
2514 static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, argument
2528 tl = intel_context_timeline_lock(ce);
2532 intel_context_enter(ce);
2534 rq = eb_throttle(eb, ce);
2550 mutex_lock(&ce->timeline->mutex);
2551 intel_context_exit(ce);
2552 mutex_unlock(&ce
2567 struct intel_context *ce = eb->context, *child; local
2618 struct intel_context *ce = eb->context, *child; local
2687 struct intel_context *ce, *child; local
[all...]
/linux-master/drivers/md/
H A Ddm-snap-persistent.c704 struct core_exception ce; local
710 ce.old_chunk = e->old_chunk;
711 ce.new_chunk = e->new_chunk;
712 write_exception(ps, ps->current_committed++, &ce);
768 struct core_exception ce; local
789 read_exception(ps, ps->area, ps->current_committed - 1, &ce);
790 *last_old_chunk = ce.old_chunk;
791 *last_new_chunk = ce.new_chunk;
800 ps->current_committed - 1 - nr_consecutive, &ce);
801 if (ce
[all...]
/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Dhuge_pages.c1055 static int gpu_write(struct intel_context *ce, argument
1068 return igt_gpu_fill_dw(ce, vma, dw * sizeof(u32),
1146 static int __igt_write_huge(struct intel_context *ce, argument
1155 vma = i915_vma_instance(obj, ce->vm, NULL);
1165 if (err == -ENOSPC && i915_is_ggtt(ce->vm))
1175 err = gpu_write(ce, vma, dword, val);
1197 struct intel_context *ce; local
1231 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1233 if (!intel_engine_can_store_dword(ce->engine))
1236 max = min(max, ce
1268 struct intel_context *ce; local
1620 struct intel_context *ce; local
1837 struct intel_context *ce; local
[all...]
/linux-master/drivers/net/wireless/ath/ath10k/
H A DMakefile25 ath10k_core-$(CONFIG_ATH10K_CE) += ce.o
H A Dsnoc.h12 #include "ce.h"
31 /* protect ce info */
74 struct ath10k_ce ce; member in struct:ath10k_snoc
/linux-master/drivers/gpu/drm/tegra/
H A Ddp.h131 * @ce: channel equalization read interval
135 unsigned int ce; member in struct:drm_dp_link::__anon385
/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_uc.h41 struct intel_context *ce; /* for submission to GSC FW via GSC engine */ member in struct:intel_gsc_uc
H A Dintel_gsc_uc_heci_cmd_submit.h90 struct intel_context *ce,
/linux-master/drivers/net/wireless/ath/ath11k/
H A DMakefile16 ce.o \
/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_abi16.h24 struct nvif_object ce; member in struct:nouveau_abi16_chan
/linux-master/drivers/clocksource/
H A Dtimer-clint.c112 struct clock_event_device *ce)
131 struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); local
133 ce->cpumask = cpumask_of(cpu);
134 clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX);
111 clint_clock_next_event(unsigned long delta, struct clock_event_device *ce) argument
/linux-master/kernel/time/
H A Dclockevents.c28 struct clock_event_device *ce; member in struct:ce_unbind
406 res = __clockevents_try_unbind(cu->ce, smp_processor_id());
408 res = clockevents_replace(cu->ce);
419 struct ce_unbind cu = { .ce = ced, .res = -ENODEV };
693 struct clock_event_device *ce = NULL, *iter; local
704 ce = iter;
710 * We hold clockevents_mutex, so ce can't go away
713 ret = clockevents_unbind(ce, dev->id);

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