Searched refs:bit_idx (Results 26 - 50 of 115) sorted by relevance

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/linux-master/drivers/clk/ti/
H A Dinterface.c30 struct clk_omap_reg *reg, u8 bit_idx,
44 clk_hw->enable_bit = bit_idx;
27 _register_interface(struct device_node *node, const char *name, const char *parent_name, struct clk_omap_reg *reg, u8 bit_idx, const struct clk_hw_omap_ops *ops) argument
/linux-master/drivers/gpio/
H A Dgpio-graniterapids.c162 unsigned int bit_idx = gpio % GNR_PINS_PER_REG; local
169 reg &= ~BIT(bit_idx);
177 unsigned int bit_idx = gpio % GNR_PINS_PER_REG; local
185 reg &= ~BIT(bit_idx);
187 reg |= BIT(bit_idx);
264 unsigned int bit_idx; local
274 for_each_set_bit(bit_idx, &pending, GNR_PINS_PER_REG) {
275 unsigned int hwirq = i * GNR_PINS_PER_REG + bit_idx;
/linux-master/drivers/clk/meson/
H A Dgxbb.c574 .bit_idx = 27,
601 .bit_idx = 28,
639 .bit_idx = 29,
665 .bit_idx = 30,
691 .bit_idx = 31,
778 .bit_idx = 14,
830 .bit_idx = 14,
873 .bit_idx = 14,
935 .bit_idx = 7,
986 .bit_idx
[all...]
H A Dmeson8b.c333 .bit_idx = 27,
361 .bit_idx = 28,
389 .bit_idx = 29,
417 .bit_idx = 30,
445 .bit_idx = 31,
510 .bit_idx = 14,
555 .bit_idx = 14,
600 .bit_idx = 14,
657 .bit_idx = 7,
839 .bit_idx
3613 u8 bit_idx; member in struct:meson8b_clk_reset_line
[all...]
H A Ds4-peripherals.c23 .bit_idx = 31,
107 .bit_idx = 30,
192 .bit_idx = 29,
238 .bit_idx = 13,
270 .bit_idx = 31,
361 .bit_idx = 30,
377 .bit_idx = 31,
468 .bit_idx = 30,
523 .bit_idx = 8,
539 .bit_idx
[all...]
H A Dgxbb-aoclk.c30 .bit_idx = (_bit), \
53 .bit_idx = 6,
68 .bit_idx = 31,
147 .bit_idx = 30,
H A Dclk-regmap.c18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx),
19 set ? BIT(gate->bit_idx) : 0);
40 val ^= BIT(gate->bit_idx);
42 val &= BIT(gate->bit_idx);
H A Ds4-pll.c102 .bit_idx = 24,
128 .bit_idx = 20,
154 .bit_idx = 21,
180 .bit_idx = 22,
206 .bit_idx = 23,
234 .bit_idx = 25,
557 .bit_idx = 31,
611 .bit_idx = 31,
665 .bit_idx = 31,
719 .bit_idx
[all...]
H A Dg12a.c223 .bit_idx = 24,
240 .bit_idx = 24,
296 .bit_idx = 24,
333 .bit_idx = 20,
1137 .bit_idx = 1,
1156 .bit_idx = 1,
1216 .bit_idx = 1,
1250 .bit_idx = 17,
1284 .bit_idx = 18,
1328 .bit_idx
[all...]
/linux-master/arch/arm/mach-ep93xx/
H A Dclock.c63 u8 bit_idx; member in struct:clk_psc
79 return (val & BIT(psc->bit_idx)) ? 1 : 0;
92 val |= BIT(psc->bit_idx);
112 val &= ~BIT(psc->bit_idx);
129 u8 bit_idx)
146 psc->bit_idx = bit_idx;
326 u8 bit_idx)
343 psc->bit_idx = bit_idx;
126 ep93xx_clk_register_gate(const char *name, const char *parent_name, void __iomem *reg, u8 bit_idx) argument
324 clk_hw_register_ddiv(const char *name, void __iomem *reg, u8 bit_idx) argument
[all...]
/linux-master/drivers/clk/
H A Dclk-stm32h7.c217 void __iomem *reg, u8 bit_idx, u8 bit_rdy,
238 rgate->gate.bit_idx = bit_idx;
253 u8 bit_idx; member in struct:gate_cfg
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, argument
342 gate->bit_idx = bit_idx;
402 cfg->gate->bit_idx,
593 u8 bit_idx; member in struct:stm32_osc_clk
603 .bit_idx
215 clk_register_ready_gate(struct device *dev, const char *name, const char *parent_name, void __iomem *reg, u8 bit_idx, u8 bit_rdy, unsigned long flags, spinlock_t *lock) argument
622 u8 bit_idx; member in struct:st32h7_pll_cfg
979 u8 bit_idx; member in struct:pclk_t
[all...]
H A Dclk-fsl-sai.c48 sai_clk->gate.bit_idx = CSR_BCE_BIT;
/linux-master/drivers/clk/sunxi/
H A Dclk-a10-mod1.c47 gate->bit_idx = SUN4I_MOD1_ENABLE;
H A Dclk-a10-hosc.c40 gate->bit_idx = SUNXI_OSC24M_GATE;
H A Dclk-a20-gmac.c84 gate->bit_idx = SUN7I_A20_GMAC_GPIT;
H A Dclk-sun4i-pll3.c45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
/linux-master/drivers/clk/renesas/
H A Drcar-cpg-lib.c157 rpc->gate.bit_idx = 8;
196 rpcd2->gate.bit_idx = 9;
/linux-master/drivers/clk/imx/
H A Dclk-gate-exclusive.c82 gate->bit_idx = shift;
H A Dclk-composite-93.c58 reg &= ~BIT(gate->bit_idx);
60 reg |= BIT(gate->bit_idx);
232 gate->bit_idx = CCM_OFF_SHIFT;
/linux-master/drivers/clk/actions/
H A Dowl-pll.c119 return !!(reg & BIT(pll_hw->bit_idx));
130 reg |= BIT(pll_hw->bit_idx);
132 reg &= ~BIT(pll_hw->bit_idx);
/linux-master/drivers/clk/keystone/
H A Dsyscon-clk.c24 u32 bit_idx; member in struct:ti_syscon_gate_clk_data
94 priv->idx = BIT(data->bit_idx);
164 .bit_idx = (_bit_idx), \
/linux-master/drivers/clk/stm32/
H A Dclk-stm32-core.c145 writel(BIT(gate->bit_idx), addr);
147 writel(readl(addr) | BIT(gate->bit_idx), addr);
153 writel(BIT(gate->bit_idx), addr + gate->set_clr);
155 writel(readl(addr) & ~BIT(gate->bit_idx), addr);
170 writel(BIT(gate->bit_idx), addr + gate->set_clr);
172 writel(readl(addr) & ~BIT(gate->bit_idx), addr);
181 return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
/linux-master/include/linux/
H A Dclk-provider.h494 * @bit_idx: single bit controlling gate
501 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
515 u8 bit_idx; member in struct:clk_gate
532 void __iomem *reg, u8 bit_idx,
539 void __iomem *reg, u8 bit_idx,
543 void __iomem *reg, u8 bit_idx,
552 * @bit_idx: which bit in the register controls gating of this clock
556 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
559 NULL, (flags), (reg), (bit_idx), \
569 * @bit_idx
[all...]
/linux-master/drivers/clk/ralink/
H A Dclk-mt7621.c58 u32 bit_idx; member in struct:mt7621_gate
67 .bit_idx = _shift \
104 clk_gate->bit_idx, clk_gate->bit_idx);
112 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0);
124 return val & clk_gate->bit_idx;
/linux-master/drivers/clk/socfpga/
H A Dclk-pll-s10.c218 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
258 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
297 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;

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