| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_hubbub.c | 40 #define REG(reg)\ macro
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| H A D | dcn35_dccg.c | 32 #define REG(reg) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dio_link_encoder.c | 47 #define REG(reg)\ macro
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| H A D | dcn31_hpo_dp_stream_encoder.c | 34 #define REG(reg)\ macro
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| H A D | dcn31_hpo_dp_link_encoder.c | 34 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 46 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 51 #define REG(reg) \ macro
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| /linux-master/arch/m68k/ifpsp060/src/ |
| H A D | isp.S | 916 # MODE and REG are taken from the EXC_OPWORD.
923 # jump to the corresponding function for each {MODE,REG} pair.
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| /linux-master/arch/sparc/kernel/ |
| H A D | pci_schizo.c | 78 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 ((unsigned long)(REG)))
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| /linux-master/drivers/hwmon/ |
| H A D | w83792d.c | 364 #define store_in_reg(REG, reg) \
380 w83792d_write_value(client, W83792D_REG_IN_##REG[nr], \
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| H A D | w83791d.c | 364 #define store_in_reg(REG, reg) \
380 w83791d_write(client, W83791D_REG_IN_##REG[nr], data->in_##reg[nr]); \
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| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 60 #define REG(reg)\ macro
170 if (REG(DOMAIN0_PG_CONFIG) == 0)
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| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 38 #define REG(reg) \ macro
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| H A D | dce_audio.c | 39 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| H A D | dce100_resource.c | 409 #define REG(reg) mm ## reg macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 59 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 104 #define REG(reg_name) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 36 #define REG(reg)\ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_cm_common.c | 32 #define REG(reg) reg macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 50 #define REG(reg_name) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 69 #define REG(reg_name) \ macro
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 58 #define REG(reg_name) \ macro
|
| /linux-master/sound/sparc/ |
| H A D | cs4231.c | 301 __cs4231_writeb(chip, value, CS4231U(chip, REG));
333 return __cs4231_readb(chip, CS4231U(chip, REG));
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| /linux-master/drivers/mmc/host/ |
| H A D | vub300.c | 221 #define REG(c) (0x01FFFF & (c->arg>>9)) macro
1859 u32 reg = REG(cmd);
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| /linux-master/drivers/net/ethernet/sun/ |
| H A D | niu.c | 150 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
152 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
|